Algorithmic bus and circuit layout for wafer-scale integration and multichip modules

In both laser-link-oriented wafer scale integration (WSI) and multichip modules (MCMs), arrays of devices may be ordered in such a way that the actual physical position of devices is extremely important. Traditional graphic-based design systems are not well suited for such applications. Examples are presented illustrating the effectiveness of a C-based design language (CDL) for WSI laser-link bus placement and MCM chip placement and interconnection. A brief description of the CDL platform is included.<>