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1993 Proceedings Fifth Annual IEEE International Conference on Wafer Scale Integration最新文献

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Dual and fail-safe redundancy for static mask-ROMs and PLAs 双和故障安全冗余静态掩码rom和pla
1993 Proceedings Fifth Annual IEEE International Conference on Wafer Scale Integration Pub Date : 1993-01-20 DOI: 10.1109/ICWSI.1993.255273
N. Tsuda
{"title":"Dual and fail-safe redundancy for static mask-ROMs and PLAs","authors":"N. Tsuda","doi":"10.1109/ICWSI.1993.255273","DOIUrl":"https://doi.org/10.1109/ICWSI.1993.255273","url":null,"abstract":"An advanced dual and fail-safe redundancy configuration for static mask-ROMs is presented. This configuration uses double coding-point cells and makes the ROM units more fail-safe by using additional fault-detection circuits. An expanded application of the proposed redundancy scheme to programmable logic arrays (PLAs) consisting of AND-ROM and OR-ROM pairs is proposed. If applied to a 256-kb ROM and a 49-k program-point PLA using 1.5- mu m CMOS technology, it is estimated that the proposed redundancy reduces the effective circuit area for defect occurrence to 16% of that of the nonredundant basic circuit module for the ROM, and to 9% for the PLA.<<ETX>>","PeriodicalId":377227,"journal":{"name":"1993 Proceedings Fifth Annual IEEE International Conference on Wafer Scale Integration","volume":"65 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-01-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124133338","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Architectures for catastrophic and delay fault tolerance 灾难性和延迟容错的体系结构
1993 Proceedings Fifth Annual IEEE International Conference on Wafer Scale Integration Pub Date : 1993-01-20 DOI: 10.1109/ICWSI.1993.255274
D. Walker
{"title":"Architectures for catastrophic and delay fault tolerance","authors":"D. Walker","doi":"10.1109/ICWSI.1993.255274","DOIUrl":"https://doi.org/10.1109/ICWSI.1993.255274","url":null,"abstract":"Wafer-scale architectures have defect tolerance as one of their primary goals. Anecdotal data and simulation experiments indicate that as geometries shrink, delay faults caused by spot defects will become increasingly important, and must be tolerated in order for wafer-scale architectures to have acceptable parametric yield. Approaches to designing architectures that possess both catastrophic and delay fault tolerance are presented.<<ETX>>","PeriodicalId":377227,"journal":{"name":"1993 Proceedings Fifth Annual IEEE International Conference on Wafer Scale Integration","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-01-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128190719","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Use of high dielectric constant insulators for bypass capacitance in WSI and wafer scale hybrid multichip modules 高介电常数绝缘体在WSI和晶圆级混合多芯片模块中的旁路电容应用
1993 Proceedings Fifth Annual IEEE International Conference on Wafer Scale Integration Pub Date : 1993-01-20 DOI: 10.1109/ICWSI.1993.255246
R. Philhower, J. Van Etten, K. Nah, C.J. Loy, C. Maier, P. Campbell, H.J. Grueb, P. Li, W. Liu, T. Lu, J. McDonald
{"title":"Use of high dielectric constant insulators for bypass capacitance in WSI and wafer scale hybrid multichip modules","authors":"R. Philhower, J. Van Etten, K. Nah, C.J. Loy, C. Maier, P. Campbell, H.J. Grueb, P. Li, W. Liu, T. Lu, J. McDonald","doi":"10.1109/ICWSI.1993.255246","DOIUrl":"https://doi.org/10.1109/ICWSI.1993.255246","url":null,"abstract":"The exceptionally large amounts of bypass-capacitance requirements of wafer scale integration (WSI) and wafer scale hybrid packaging/multichip module (WSHP/MCM) based systems operating at state-of-the-art switching speeds are explored. The capacitance required may become considerably larger than can be obtained by simply making thin-oxide-metal-plate capacitors unless alternate design styles which exhibit less switching noise are adopted for the circuits employed. Some of the criteria for picking the value of the bypass capacitance are examined, together with techniques for introducing high-dielectric-constant materials into the processing of the semiconductor substrates. The possibility of depositing thin layers of amorphous BaTiO/sub 3/ at low temperature to form a reliable, pin-hole free dielectric for bypass capacitance by use of ionized cluster beam techniques is explored. Deposition of the amorphous material on both metal and semiconductor substrates is possible.<<ETX>>","PeriodicalId":377227,"journal":{"name":"1993 Proceedings Fifth Annual IEEE International Conference on Wafer Scale Integration","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-01-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114443860","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Effect of communication delay on gracefully degradable WSI processor array performance 通信延迟对优雅可降解WSI处理器阵列性能的影响
1993 Proceedings Fifth Annual IEEE International Conference on Wafer Scale Integration Pub Date : 1993-01-20 DOI: 10.1109/ICWSI.1993.255260
D. Landis, N. Nigam
{"title":"Effect of communication delay on gracefully degradable WSI processor array performance","authors":"D. Landis, N. Nigam","doi":"10.1109/ICWSI.1993.255260","DOIUrl":"https://doi.org/10.1109/ICWSI.1993.255260","url":null,"abstract":"Online reconfiguration of wafer scale integration (WSI) processor arrays provides graceful degradation of performance in the presence of failed processors. Each time a processor fails, soft switching can be used to bypass either a row or column and a degraded performance functional array can be maintained. Processor to processor communication delay may increase with each processor failure, and the entire array will eventually fail if the delay exceeds a predetermined limit. The impact of reconfiguration on fault tolerant WSI processor array performance is examined. The analysis considers interconnect length, communication delay, and maximum operating frequency.<<ETX>>","PeriodicalId":377227,"journal":{"name":"1993 Proceedings Fifth Annual IEEE International Conference on Wafer Scale Integration","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-01-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115593888","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Interface design optimisation for WASP devices WASP设备的接口设计优化
1993 Proceedings Fifth Annual IEEE International Conference on Wafer Scale Integration Pub Date : 1993-01-20 DOI: 10.1109/ICWSI.1993.255256
H. Bolouri, M. Hussaini, S. Hedge, R. Lea
{"title":"Interface design optimisation for WASP devices","authors":"H. Bolouri, M. Hussaini, S. Hedge, R. Lea","doi":"10.1109/ICWSI.1993.255256","DOIUrl":"https://doi.org/10.1109/ICWSI.1993.255256","url":null,"abstract":"Details of defect and fault tolerance strategies used in the wafer interface blocks of wafer scale integration (WSI) associative string processor (WASP) devices are given. A structured approach to the design and optimization of redundant-path defect- and fault-tolerant signal distribution networks is presented. Monte Carlo simulations are used to analyze the success rate of various WASP signal distribution network topologies in the presence of randomly distributed defects. It is shown that the proposed signal distribution strategy lends itself well to high-speed recovery from in-operation failures.<<ETX>>","PeriodicalId":377227,"journal":{"name":"1993 Proceedings Fifth Annual IEEE International Conference on Wafer Scale Integration","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-01-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126588586","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Application opportunities for hybrid-WSI 混合wsi的应用机会
1993 Proceedings Fifth Annual IEEE International Conference on Wafer Scale Integration Pub Date : 1993-01-20 DOI: 10.1109/ICWSI.1993.255265
D. Ming, R. Scannell
{"title":"Application opportunities for hybrid-WSI","authors":"D. Ming, R. Scannell","doi":"10.1109/ICWSI.1993.255265","DOIUrl":"https://doi.org/10.1109/ICWSI.1993.255265","url":null,"abstract":"The performance, small size, and potentially lower cost of wafer scale integration (WSI) offers opportunities currently not being addressed optimally. In many data processing situations, data are recorded on site at the sensor input while the processing of the data is done at a remote site. With the advantages of WSI, data processing can be brought out of the laboratory and into the field. Thus real-time data analysis can be achieved, while also reducing costs and improving efficiency. A description is given of some of the first applications, namely, interceptor processors for avionics.<<ETX>>","PeriodicalId":377227,"journal":{"name":"1993 Proceedings Fifth Annual IEEE International Conference on Wafer Scale Integration","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-01-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132550578","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Active silicon substrate technology for miniaturized ultra high performance processing 微型化超高性能加工的有源硅衬底技术
1993 Proceedings Fifth Annual IEEE International Conference on Wafer Scale Integration Pub Date : 1993-01-20 DOI: 10.1109/ICWSI.1993.255243
H. Malek, R. Pearson
{"title":"Active silicon substrate technology for miniaturized ultra high performance processing","authors":"H. Malek, R. Pearson","doi":"10.1109/ICWSI.1993.255243","DOIUrl":"https://doi.org/10.1109/ICWSI.1993.255243","url":null,"abstract":"A multichip module (MCM) technology called active silicon substrate (ASIS) that raises architectural design of signal/data processing systems to much higher levels of microminiaturization and performance is described. The merits of active substrates over the conventional passive ones are demonstrated through the implementation of several features that are possible when active elements are embedded in the interconnecting substrate and mounting platform. These include scalable fault-tolerant computing elements, replaceable drivers/buffers, and embedded local/global self-test circuits. The ASIS technology allows more than one type of processing architecture to be embedded and integrated in the same substrate, thus providing a viable approach for water scale integration.<<ETX>>","PeriodicalId":377227,"journal":{"name":"1993 Proceedings Fifth Annual IEEE International Conference on Wafer Scale Integration","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-01-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133440513","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Bond failures on hybrid-WSI substrates 混合wsi衬底上的键合失效
1993 Proceedings Fifth Annual IEEE International Conference on Wafer Scale Integration Pub Date : 1993-01-20 DOI: 10.1109/ICWSI.1993.255248
C. Habiger
{"title":"Bond failures on hybrid-WSI substrates","authors":"C. Habiger","doi":"10.1109/ICWSI.1993.255248","DOIUrl":"https://doi.org/10.1109/ICWSI.1993.255248","url":null,"abstract":"Modern hybrid wafer scale integration (HWSI) devices increasingly employ flip-chip bonding. Thermal cycling tests do not model the true operating conditions of HWSI devices, as the differences in operating temperatures of chips and substrate are neglected. These temperature differences resemble the most important thermal bond failure mechanism. An approach to the modeling of true operating conditions is presented, and its impact on the reliability of flip-chip bonds in silicon-on-silicon assemblies is assessed.<<ETX>>","PeriodicalId":377227,"journal":{"name":"1993 Proceedings Fifth Annual IEEE International Conference on Wafer Scale Integration","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-01-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129470194","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
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