Effect of communication delay on gracefully degradable WSI processor array performance

Abstract

Online reconfiguration of wafer scale integration (WSI) processor arrays provides graceful degradation of performance in the presence of failed processors. Each time a processor fails, soft switching can be used to bypass either a row or column and a degraded performance functional array can be maintained. Processor to processor communication delay may increase with each processor failure, and the entire array will eventually fail if the delay exceeds a predetermined limit. The impact of reconfiguration on fault tolerant WSI processor array performance is examined. The analysis considers interconnect length, communication delay, and maximum operating frequency.<>