Architectures for catastrophic and delay fault tolerance

Abstract

Wafer-scale architectures have defect tolerance as one of their primary goals. Anecdotal data and simulation experiments indicate that as geometries shrink, delay faults caused by spot defects will become increasingly important, and must be tolerated in order for wafer-scale architectures to have acceptable parametric yield. Approaches to designing architectures that possess both catastrophic and delay fault tolerance are presented.<>