发布求助
文献互助 智能选刊 最新文献

1993 Proceedings Fifth Annual IEEE International Conference on Wafer Scale Integration最新文献

筛选
英文 中文
3D wafer stack neurocomputing 3D晶圆堆叠神经计算
1993 Proceedings Fifth Annual IEEE International Conference on Wafer Scale Integration Pub Date : 1993-01-20 DOI: 10.1109/ICWSI.1993.255272
M. Campbell, S. T. Toborg, S.L. Taylor
{"title":"3D wafer stack neurocomputing","authors":"M. Campbell, S. T. Toborg, S.L. Taylor","doi":"10.1109/ICWSI.1993.255272","DOIUrl":"https://doi.org/10.1109/ICWSI.1993.255272","url":null,"abstract":"A family of massively parallel multiple-single-instruction multiple-data (MSIMD) architectures which can be configured to efficiently handle a variety of different neural network models is introduced. The underlying technology is three dimensional wafer scale integration (3D WSI), which provides an ideal medium for constructing low-power hardware tailored for neural network processing. The performance of this prototype is compared with that of enhanced architectures configured with special wafer types to accelerate neural network operations. The design emphasizes the synergy between neural processing functions and the 3D WSI architecture and packaging. Detailed microcode emulations are used to access the impact of different algorithms and architecture modifications. Neural networks for cooperative vision integration and multilayer backpropagation are mapped onto various 3-D wafer stacks.<<ETX>>","PeriodicalId":377227,"journal":{"name":"1993 Proceedings Fifth Annual IEEE International Conference on Wafer Scale Integration","volume":"98 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-01-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114851225","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
The GE high density overlay MCM interconnect method solves high power needs of GaAs system design GE高密度叠加MCM互连方法解决了GaAs系统设计的高功率需求
1993 Proceedings Fifth Annual IEEE International Conference on Wafer Scale Integration Pub Date : 1993-01-20 DOI: 10.1109/ICWSI.1993.255244
M. Gdula, A. Yerman, V. Krishnamurthy, R. Fillion
{"title":"The GE high density overlay MCM interconnect method solves high power needs of GaAs system design","authors":"M. Gdula, A. Yerman, V. Krishnamurthy, R. Fillion","doi":"10.1109/ICWSI.1993.255244","DOIUrl":"https://doi.org/10.1109/ICWSI.1993.255244","url":null,"abstract":"As electronic systems signals and clock rates exceed 100 MHz, designers must consider the use of emerging high performance digital GaAs chip technology. Because GaAs parts do not yield at the high rates of more mature silicon technology devices, it is presently infeasible to build monolithic wafer scale integration (WSI) with GaAs technology. A hybrid wafer scale integration (HWSI) approach has been developed to overcome the limits of monolithic approaches, including the ability to provide for multichip module (MCM) process optimizations serving low IR loss requirements for power delivery, and use of overlay interconnect, first placing the chip into a structure for the most advantageous thermal management.<<ETX>>","PeriodicalId":377227,"journal":{"name":"1993 Proceedings Fifth Annual IEEE International Conference on Wafer Scale Integration","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-01-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126039086","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A comparative study of clock distribution approaches for WSI WSI时钟分布方法的比较研究
1993 Proceedings Fifth Annual IEEE International Conference on Wafer Scale Integration Pub Date : 1993-01-20 DOI: 10.1109/ICWSI.1993.255254
N. Nigam, C. Keezer
{"title":"A comparative study of clock distribution approaches for WSI","authors":"N. Nigam, C. Keezer","doi":"10.1109/ICWSI.1993.255254","DOIUrl":"https://doi.org/10.1109/ICWSI.1993.255254","url":null,"abstract":"Five different designs for a hypothetical five-inch wafer with an array of 8*8 cells are presented. The networks are simulated using HSPICE for comparison of power dissipation, delay, and skew. It is found that the large physical dimensions of a wafer scale system require that the signal interconnections be treated as transmission lines with finite delays in order to provide an accurate simulation of the signal wave shapes and timing. When clock distributions networks are compared, it is found that for a given power budget a tradeoff between delay and skew can be made. If a total power budget is established for the clock distribution network, then the five methods can be compared as to signal propagation delays and skew.<<ETX>>","PeriodicalId":377227,"journal":{"name":"1993 Proceedings Fifth Annual IEEE International Conference on Wafer Scale Integration","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-01-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131064418","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
A full experience of designing a wafer scale 2D array 具有设计晶圆级二维阵列的丰富经验
1993 Proceedings Fifth Annual IEEE International Conference on Wafer Scale Integration Pub Date : 1993-01-20 DOI: 10.1109/ICWSI.1993.255275
A. Boubekeur, J. Patry, G. Saucier, M. Slimane-kadi, J. Trilhe
{"title":"A full experience of designing a wafer scale 2D array","authors":"A. Boubekeur, J. Patry, G. Saucier, M. Slimane-kadi, J. Trilhe","doi":"10.1109/ICWSI.1993.255275","DOIUrl":"https://doi.org/10.1109/ICWSI.1993.255275","url":null,"abstract":"The design of a wafer scale 2D array called ELSA (European large single instruction, multiple data (SIMD) array) is given. Software methods and tools as well as hardware switching devices used to achieve defect tolerance and create a defect-free 2D array are described. ELSA is implemented in 1.2- mu m CMOS technology and has been studied within an ESPRIT project on wafer scale integration.<<ETX>>","PeriodicalId":377227,"journal":{"name":"1993 Proceedings Fifth Annual IEEE International Conference on Wafer Scale Integration","volume":"102 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-01-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133997444","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
WSI clock and signal distribution: a novel approach WSI时钟和信号分配:一种新颖的方法
1993 Proceedings Fifth Annual IEEE International Conference on Wafer Scale Integration Pub Date : 1993-01-20 DOI: 10.1109/ICWSI.1993.255253
N.G. Sheridan, C. Habiger, R. Lea
{"title":"WSI clock and signal distribution: a novel approach","authors":"N.G. Sheridan, C. Habiger, R. Lea","doi":"10.1109/ICWSI.1993.255253","DOIUrl":"https://doi.org/10.1109/ICWSI.1993.255253","url":null,"abstract":"Wafer scale integration (WSI) is a technology of particular interest for applications with severe size, weight, power, cost and reliability requirements. Because of technological difficulties in implementing clock and signal distribution, monolithic WSI has not been widely employed. A novel approach to clock and signal distribution for WSI is introduced. It combines the advantages of monolithic-WSI with the superior interconnection capabilities of hybrid-WSI.<<ETX>>","PeriodicalId":377227,"journal":{"name":"1993 Proceedings Fifth Annual IEEE International Conference on Wafer Scale Integration","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-01-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133611650","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
The efficient design of a strongly fault-secure ALU using a reduced Berger code for WSI processor arrays 高效设计的强故障安全ALU使用减少的伯杰码为WSI处理器阵列
1993 Proceedings Fifth Annual IEEE International Conference on Wafer Scale Integration Pub Date : 1993-01-20 DOI: 10.1109/ICWSI.1993.255262
J.H. Kim, T. Rao, G. Feng, Jien-Chung Lo
{"title":"The efficient design of a strongly fault-secure ALU using a reduced Berger code for WSI processor arrays","authors":"J.H. Kim, T. Rao, G. Feng, Jien-Chung Lo","doi":"10.1109/ICWSI.1993.255262","DOIUrl":"https://doi.org/10.1109/ICWSI.1993.255262","url":null,"abstract":"Due to their operative nature, arithmetic and logic units (ALUs) are the most difficult functional circuits to check among the components of a processor. The efficient design of a 32-b strongly-fault-secure (SFS) ALU using a reduced Berger code is presented. The reduced Berger code encodes both operands and the computation results, and uses only the two least significant check bits of its Berger code counterpart regardless of information length. The application of reduced Berger code yields more efficient implementation of a strongly-fault-secure ALU than the previously proposed techniques.<<ETX>>","PeriodicalId":377227,"journal":{"name":"1993 Proceedings Fifth Annual IEEE International Conference on Wafer Scale Integration","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-01-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130209055","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Memory-based reasoning implemented by wafer scale integration 晶圆级集成实现的基于记忆的推理
1993 Proceedings Fifth Annual IEEE International Conference on Wafer Scale Integration Pub Date : 1993-01-20 DOI: 10.1109/ICWSI.1993.255278
M. Yasunaga, H. Kitano
{"title":"Memory-based reasoning implemented by wafer scale integration","authors":"M. Yasunaga, H. Kitano","doi":"10.1109/ICWSI.1993.255278","DOIUrl":"https://doi.org/10.1109/ICWSI.1993.255278","url":null,"abstract":"The high robustness of memory-based reasoning (MBR), which is suitable for hardware implementation using wafer scale integration (WSI) technology, is demonstrated. A WSI MBR hardware design is proposed. Its robustness is evaluated by a WSI MBR simulator. The results show that defects or other fluctuations of device parameters have only minor impacts on the performances of the MBR. It is found that in order to obtain higher reasoning accuracy, the size of the MBR database is much more crucial than the computation resolution. The proposed WSI MBR processor takes advantage of benefits discovered in the simulation results.<<ETX>>","PeriodicalId":377227,"journal":{"name":"1993 Proceedings Fifth Annual IEEE International Conference on Wafer Scale Integration","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-01-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132555540","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Optimizing real-time fault tolerance design in WSI 优化WSI实时容错设计
1993 Proceedings Fifth Annual IEEE International Conference on Wafer Scale Integration Pub Date : 1993-01-20 DOI: 10.1109/ICWSI.1993.255263
J. Samson
{"title":"Optimizing real-time fault tolerance design in WSI","authors":"J. Samson","doi":"10.1109/ICWSI.1993.255263","DOIUrl":"https://doi.org/10.1109/ICWSI.1993.255263","url":null,"abstract":"An overview of real-time fault tolerance performance issues is provided, and a systematic approach to the optimization of real-time fault tolerance design in VLSI and wafer scale architectures is described and illustrated. The approach is based on the identification of fundamental optimization metrics, represented by simple product and quotient (reciprocal product) relationships, which extend traditional cost/benefit analysis to real-time fault tolerance in VLSI and wafer scale architectures and systems.<<ETX>>","PeriodicalId":377227,"journal":{"name":"1993 Proceedings Fifth Annual IEEE International Conference on Wafer Scale Integration","volume":"68 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-01-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127032220","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Silicon MCMs for parallel computing applications 用于并行计算应用的硅mcm
1993 Proceedings Fifth Annual IEEE International Conference on Wafer Scale Integration Pub Date : 1993-01-20 DOI: 10.1109/ICWSI.1993.255267
M. McLaren, I. Jamison
{"title":"Silicon MCMs for parallel computing applications","authors":"M. McLaren, I. Jamison","doi":"10.1109/ICWSI.1993.255267","DOIUrl":"https://doi.org/10.1109/ICWSI.1993.255267","url":null,"abstract":"Multichip module (MCM) technology is used in the design of large-scale, distributed memory, multiple-instruction, multiple-data (MIMD) processors. Two demonstrators have been selected for different applications within a parallel computer. The applications stress various aspects of the technology. The demonstrators are the design of high-performance processing nodes, and the construction of multistage switching networks. In both cases, implementations exist using conventional packaging technology, affording the opportunity to directly compare the performance of the solutions with respect to cost and various other design criteria.<<ETX>>","PeriodicalId":377227,"journal":{"name":"1993 Proceedings Fifth Annual IEEE International Conference on Wafer Scale Integration","volume":"35 Suppl 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-01-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134067143","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A fault-tolerant multi-port associative memory scheme 一种容错多端口关联内存方案
1993 Proceedings Fifth Annual IEEE International Conference on Wafer Scale Integration Pub Date : 1993-01-20 DOI: 10.1109/ICWSI.1993.255271
L. Dadda, M. Sami, R. Stefanelli
{"title":"A fault-tolerant multi-port associative memory scheme","authors":"L. Dadda, M. Sami, R. Stefanelli","doi":"10.1109/ICWSI.1993.255271","DOIUrl":"https://doi.org/10.1109/ICWSI.1993.255271","url":null,"abstract":"A multiport associative memory allowing independent and simultaneous access from the two ports is described. The device is conceived as part of a complex digital system designed for calorimetry at CERN's large Hadron Collider, so that system requirements dictate functional specification of the memory. Ad hoc fault tolerance policies, supporting both permanent and transient fault treatment, are introduced to account for the severe environment in which the system will operate.<<ETX>>","PeriodicalId":377227,"journal":{"name":"1993 Proceedings Fifth Annual IEEE International Conference on Wafer Scale Integration","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-01-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121772995","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
首页 上一页 下一页 尾页
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整，为了账户安全，请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
请完成安全验证×
相关产品
×
本文献相关产品
联系我们：info@booksci.cn Book学术提供免费学术资源搜索服务，方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号：481959085
Book学术官方微信