高效设计的强故障安全ALU使用减少的伯杰码为WSI处理器阵列

1993 Proceedings Fifth Annual IEEE International Conference on Wafer Scale Integration Pub Date : 1993-01-20 DOI:10.1109/ICWSI.1993.255262

J.H. Kim, T. Rao, G. Feng, Jien-Chung Lo

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引用次数: 3

摘要

算术和逻辑单元(alu)由于其操作性质，是处理器组件中最难检查的功能电路。提出了一种采用简化Berger码的32b强故障安全(SFS) ALU的高效设计方法。简化后的伯杰码对操作数和计算结果进行编码，并且不管信息长度如何，只使用伯杰码对应的两个最低有效校验位。与之前提出的技术相比，减少Berger代码的应用可以更有效地实现强故障安全ALU。

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The efficient design of a strongly fault-secure ALU using a reduced Berger code for WSI processor arrays

Due to their operative nature, arithmetic and logic units (ALUs) are the most difficult functional circuits to check among the components of a processor. The efficient design of a 32-b strongly-fault-secure (SFS) ALU using a reduced Berger code is presented. The reduced Berger code encodes both operands and the computation results, and uses only the two least significant check bits of its Berger code counterpart regardless of information length. The application of reduced Berger code yields more efficient implementation of a strongly-fault-secure ALU than the previously proposed techniques.<>

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1993 Proceedings Fifth Annual IEEE International Conference on Wafer Scale Integration

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