A comparative study of clock distribution approaches for WSI

Abstract

Five different designs for a hypothetical five-inch wafer with an array of 8*8 cells are presented. The networks are simulated using HSPICE for comparison of power dissipation, delay, and skew. It is found that the large physical dimensions of a wafer scale system require that the signal interconnections be treated as transmission lines with finite delays in order to provide an accurate simulation of the signal wave shapes and timing. When clock distributions networks are compared, it is found that for a given power budget a tradeoff between delay and skew can be made. If a total power budget is established for the clock distribution network, then the five methods can be compared as to signal propagation delays and skew.<>