A. Boubekeur, J. Patry, G. Saucier, M. Slimane-kadi, J. Trilhe
{"title":"具有设计晶圆级二维阵列的丰富经验","authors":"A. Boubekeur, J. Patry, G. Saucier, M. Slimane-kadi, J. Trilhe","doi":"10.1109/ICWSI.1993.255275","DOIUrl":null,"url":null,"abstract":"The design of a wafer scale 2D array called ELSA (European large single instruction, multiple data (SIMD) array) is given. Software methods and tools as well as hardware switching devices used to achieve defect tolerance and create a defect-free 2D array are described. ELSA is implemented in 1.2- mu m CMOS technology and has been studied within an ESPRIT project on wafer scale integration.<<ETX>>","PeriodicalId":377227,"journal":{"name":"1993 Proceedings Fifth Annual IEEE International Conference on Wafer Scale Integration","volume":"102 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1993-01-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"7","resultStr":"{\"title\":\"A full experience of designing a wafer scale 2D array\",\"authors\":\"A. Boubekeur, J. Patry, G. Saucier, M. Slimane-kadi, J. Trilhe\",\"doi\":\"10.1109/ICWSI.1993.255275\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The design of a wafer scale 2D array called ELSA (European large single instruction, multiple data (SIMD) array) is given. Software methods and tools as well as hardware switching devices used to achieve defect tolerance and create a defect-free 2D array are described. ELSA is implemented in 1.2- mu m CMOS technology and has been studied within an ESPRIT project on wafer scale integration.<<ETX>>\",\"PeriodicalId\":377227,\"journal\":{\"name\":\"1993 Proceedings Fifth Annual IEEE International Conference on Wafer Scale Integration\",\"volume\":\"102 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1993-01-20\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"7\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"1993 Proceedings Fifth Annual IEEE International Conference on Wafer Scale Integration\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICWSI.1993.255275\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"1993 Proceedings Fifth Annual IEEE International Conference on Wafer Scale Integration","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICWSI.1993.255275","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 7
摘要
给出了一种称为ELSA(欧洲大型单指令多数据(SIMD)阵列)的圆片级二维阵列的设计。描述了用于实现缺陷容限和创建无缺陷二维阵列的软件方法和工具以及硬件开关设备。ELSA在1.2 μ m CMOS技术中实现,并在ESPRIT晶圆级集成项目中进行了研究
A full experience of designing a wafer scale 2D array
The design of a wafer scale 2D array called ELSA (European large single instruction, multiple data (SIMD) array) is given. Software methods and tools as well as hardware switching devices used to achieve defect tolerance and create a defect-free 2D array are described. ELSA is implemented in 1.2- mu m CMOS technology and has been studied within an ESPRIT project on wafer scale integration.<>