{"title":"WASP - 3处理器的开发","authors":"I. Jalowiecki, S. Hedge, R. Williams","doi":"10.1109/ICWSI.1993.255277","DOIUrl":null,"url":null,"abstract":"The ASP (associative string processor) is a massively parallel, fault tolerant, fully associative processor designed for the implementation of very compact, easily extensible, modular low-multiple-instruction, multiple-data/high-single-instruction multiple-data (low-MIMD/high-SIMD) parallel processing systems. It is capable of supporting real-world applications of continuous data input and tightly integrated numeric and symbolic computations. The ASP module architecture and the wafer-scale (WASP-3) concept are described.<<ETX>>","PeriodicalId":377227,"journal":{"name":"1993 Proceedings Fifth Annual IEEE International Conference on Wafer Scale Integration","volume":"56 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1993-01-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"15","resultStr":"{\"title\":\"The development of the WASP 3 processor\",\"authors\":\"I. Jalowiecki, S. Hedge, R. Williams\",\"doi\":\"10.1109/ICWSI.1993.255277\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The ASP (associative string processor) is a massively parallel, fault tolerant, fully associative processor designed for the implementation of very compact, easily extensible, modular low-multiple-instruction, multiple-data/high-single-instruction multiple-data (low-MIMD/high-SIMD) parallel processing systems. It is capable of supporting real-world applications of continuous data input and tightly integrated numeric and symbolic computations. The ASP module architecture and the wafer-scale (WASP-3) concept are described.<<ETX>>\",\"PeriodicalId\":377227,\"journal\":{\"name\":\"1993 Proceedings Fifth Annual IEEE International Conference on Wafer Scale Integration\",\"volume\":\"56 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1993-01-20\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"15\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"1993 Proceedings Fifth Annual IEEE International Conference on Wafer Scale Integration\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICWSI.1993.255277\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"1993 Proceedings Fifth Annual IEEE International Conference on Wafer Scale Integration","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICWSI.1993.255277","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
The ASP (associative string processor) is a massively parallel, fault tolerant, fully associative processor designed for the implementation of very compact, easily extensible, modular low-multiple-instruction, multiple-data/high-single-instruction multiple-data (low-MIMD/high-SIMD) parallel processing systems. It is capable of supporting real-world applications of continuous data input and tightly integrated numeric and symbolic computations. The ASP module architecture and the wafer-scale (WASP-3) concept are described.<>