A testing approach for WSI globally interconnected parallel architectures

A testability analysis and a testing approach for interconnection topologies are presented. The testing approach is based on the analysis of controllability and observability of the architecture, given the cells functions and the interconnection topology. For the architectures directly derived from a data flow graph, a functional fault model is adopted. A specific fault model is derived for multistage interconnection networks. The switching matrices can be in a number of different states, depending on the number of input/output lines. In general, only a small number of states is necessary for correct computation, and these are the only states considered legal. A cell is defined to be faulty if its switching matrix can reach a nonlegal state.<>