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2021 19th IEEE International New Circuits and Systems Conference (NEWCAS)最新文献

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A Novel RF Spectrum Monitoring Architecture for an Ultra-Low-Power Wi-Fi Geopositioning System 一种用于超低功耗Wi-Fi地理定位系统的新型射频频谱监测架构
2021 19th IEEE International New Circuits and Systems Conference (NEWCAS) Pub Date : 2021-06-13 DOI: 10.1109/NEWCAS50681.2021.9462768
Naci Pekcokguler, M. Maman, A. Burg, C. Dehollain, D. Morche
{"title":"A Novel RF Spectrum Monitoring Architecture for an Ultra-Low-Power Wi-Fi Geopositioning System","authors":"Naci Pekcokguler, M. Maman, A. Burg, C. Dehollain, D. Morche","doi":"10.1109/NEWCAS50681.2021.9462768","DOIUrl":"https://doi.org/10.1109/NEWCAS50681.2021.9462768","url":null,"abstract":"Wireless radio consumes the highest power in many systems and must be activated wisely to save power especially in battery-powered systems. Hence, gathering insight into the spectrum activity is needed to control the wireless radio. In this work, classic full-band Fast Fourier Transform (FFT) and sequential digital spectrum scanning systems are presented with their high energy consumption and latency drawbacks. A context-aware, multi-layer-duty-cycled, multi-channel, ultra-low-power analog spectrum monitoring architecture is proposed as a solution to the drawbacks of the classic systems with the emphasis on Wi-Fi signal detection for a Basic Service Set Identifier (BSSID)-based geopositioning shipment tracking application. The proposed architecture provides more than 3 order of magnitude power saving in detection compared to the classic sequential spectrum scanning while maintaining the full functionality under vast variety of operating conditions.","PeriodicalId":373745,"journal":{"name":"2021 19th IEEE International New Circuits and Systems Conference (NEWCAS)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131374756","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Securing IoT/IIoT from Software Attacks Targeting Hardware Vulnerabilities 保护IoT/IIoT免受针对硬件漏洞的软件攻击
2021 19th IEEE International New Circuits and Systems Conference (NEWCAS) Pub Date : 2021-06-13 DOI: 10.1109/NEWCAS50681.2021.9462776
Nikolaos Foivos Polychronou, Pierre-Henri Thevenon, Maxime Puys, V. Beroulle
{"title":"Securing IoT/IIoT from Software Attacks Targeting Hardware Vulnerabilities","authors":"Nikolaos Foivos Polychronou, Pierre-Henri Thevenon, Maxime Puys, V. Beroulle","doi":"10.1109/NEWCAS50681.2021.9462776","DOIUrl":"https://doi.org/10.1109/NEWCAS50681.2021.9462776","url":null,"abstract":"The microarchitecture of modern systems become more and more complicated. This increasing complexity gives rise to a new class of attacks which uses software code and targets hardware vulnerabilities of the system microarchitectures. Software attacks targeting hardware vulnerabilities (SATHVs) gain popularity. In particular, cache side channel attacks, Spectre, and Rowhammer are serious threats. They take advantage of microarchitectural vulnerabilities to extract secret information or harm the system. As these attacks target the system’s hardware, they can avoid traditional software antivirus protections. However, they modify the normal operation of the system’s hardware. Hardware Performance Counters (HPCs) are special registers that allow counting specific hardware events. These registers can help us monitor system’s execution at hardware level and detect this set of attacks. Many solutions in the literature use HPCs to detect SATHVs. Although, these solutions target detecting only a limited set of the available SATHVs. If security designers do not consider all the possibilities, attackers can bypass existing protections using SATHV variants. In this article, we investigate how the side effect selection proposed in the literature, could or could not help us detect the studied attacks in our testing platform. Our threat model includes Cache side channel and Rowhammer attacks. We also discuss the limitations of software monitoring and how hardware approaches can resolve them.","PeriodicalId":373745,"journal":{"name":"2021 19th IEEE International New Circuits and Systems Conference (NEWCAS)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133753627","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Subthreshold neuromorphic devices for Spiking Neural Networks applied to embedded A.I 应用于嵌入式人工智能的脉冲神经网络阈下神经形态装置
2021 19th IEEE International New Circuits and Systems Conference (NEWCAS) Pub Date : 2021-06-13 DOI: 10.1109/NEWCAS50681.2021.9462779
C. Loyez, K. Carpentier, I. Sourikopoulos, F. Danneville
{"title":"Subthreshold neuromorphic devices for Spiking Neural Networks applied to embedded A.I","authors":"C. Loyez, K. Carpentier, I. Sourikopoulos, F. Danneville","doi":"10.1109/NEWCAS50681.2021.9462779","DOIUrl":"https://doi.org/10.1109/NEWCAS50681.2021.9462779","url":null,"abstract":"Energy autonomy is one of the major challenges of embedded Artificial Intelligence. Among the candidate technologies likely to take up such a challenge, spiking neural networks are the most promising because of both their spatio-temporal and sparse representation of the information. In this context, this paper presents a neuromorphic approach based on an industrial CMOS technology and adopting an entirely subthreshold mode of operation (supply voltage VDD lower than the MOSFET threshold voltage). The detailed topologies of fabricated artificial neurons and synapses are presented as well as experimental results, validating an energy consumption of the order of a few femto-Joules per spike. Also, an arrangement of neurons and synapses is proposed to qualify experimentally this subthreshold approach in the perspective of highly energy efficient spiking neural networks.","PeriodicalId":373745,"journal":{"name":"2021 19th IEEE International New Circuits and Systems Conference (NEWCAS)","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130442556","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
mm-Wave Single-Pole Double-Throw switches: HBT- vs MOSFET-based designs 毫米波单极双掷开关:基于HBT与基于mosfet的设计
2021 19th IEEE International New Circuits and Systems Conference (NEWCAS) Pub Date : 2021-06-13 DOI: 10.1109/NEWCAS50681.2021.9462753
M. Margalef-Rovira, C. Gaquière, A. A. L. Souza, L. Vincent, M. Barragán, E. Pistono, F. Podevin, P. Ferrari
{"title":"mm-Wave Single-Pole Double-Throw switches: HBT- vs MOSFET-based designs","authors":"M. Margalef-Rovira, C. Gaquière, A. A. L. Souza, L. Vincent, M. Barragán, E. Pistono, F. Podevin, P. Ferrari","doi":"10.1109/NEWCAS50681.2021.9462753","DOIUrl":"https://doi.org/10.1109/NEWCAS50681.2021.9462753","url":null,"abstract":"This paper aims to compare the performance of HBT-based and MOSFET-based mm-Wave SPDT switches in a single BiCMOS technology. To the best of authors’ knowledge, a direct comparison of this function in the same integrated process has never been reported before. Measurement results on two 50-GHz integrated SPDTs reveal that the HBT-based SPDT switch yields 1.7 dB of insertion loss and 14 dB of isolation in its central frequency, with a bandwidth covering the 30-80 GHz frequency range when considering a return loss greater than 10 dB. On the other hand, the MOSFET-based SPDT switch yields 2.1 dB of insertion loss and 12 dB of isolation at center frequency and a bandwidth covering the 33-80 GHz frequency range.","PeriodicalId":373745,"journal":{"name":"2021 19th IEEE International New Circuits and Systems Conference (NEWCAS)","volume":"21 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123552084","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Ultra Low Voltage Sub-100 mV Vdd CMOS 超低电压低于100 mV Vdd CMOS
2021 19th IEEE International New Circuits and Systems Conference (NEWCAS) Pub Date : 2021-06-13 DOI: 10.1109/NEWCAS50681.2021.9462735
S. Aunet
{"title":"Ultra Low Voltage Sub-100 mV Vdd CMOS","authors":"S. Aunet","doi":"10.1109/NEWCAS50681.2021.9462735","DOIUrl":"https://doi.org/10.1109/NEWCAS50681.2021.9462735","url":null,"abstract":"Logic and memory proven in silicon, operating at sub-100 mV Vdds are discussed. Static CMOS is likely to be augmented with Schmitt-trigger based solutions, especially for memories that should operate at Vdds below 100 mV.","PeriodicalId":373745,"journal":{"name":"2021 19th IEEE International New Circuits and Systems Conference (NEWCAS)","volume":"71 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123588962","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Mitigation of Mutual Pulling in Two Phase-locked Loops 两个锁相环中相互拉动的缓解
2021 19th IEEE International New Circuits and Systems Conference (NEWCAS) Pub Date : 2021-06-13 DOI: 10.1109/NEWCAS50681.2021.9462795
T. Yoshimura
{"title":"Mitigation of Mutual Pulling in Two Phase-locked Loops","authors":"T. Yoshimura","doi":"10.1109/NEWCAS50681.2021.9462795","DOIUrl":"https://doi.org/10.1109/NEWCAS50681.2021.9462795","url":null,"abstract":"In this study, we analyzed the output phase of two mutually coupled phase-locked loops (PLLs) based on the numerical calculation of nonlinear equations. According to the results, when the two PLLs were completely synchronized, the circuits became unstable owing to mutual coupling in certain timing conditions. When the frequencies of PLLs were slightly different, the behavior of phase error depended on the frequency difference. The test circuit was fabricated through a 0.18 µm CMOS process, and the measured results were compared with the theoretical results. We confirmed the mitigation of mutual pulling in synchronous PLLs by adjusting the timing between the PLLs and observed two different modes of the phase error generation under the quasi-synchronous condition in the PLLs.","PeriodicalId":373745,"journal":{"name":"2021 19th IEEE International New Circuits and Systems Conference (NEWCAS)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128812899","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Minimum Supply Voltage of 2.45 GHz LC Oscillator in 28 nm FD-SOI Process 28nm FD-SOI制程中2.45 GHz LC振荡器的最小供电电压
2021 19th IEEE International New Circuits and Systems Conference (NEWCAS) Pub Date : 2021-06-13 DOI: 10.1109/NEWCAS50681.2021.9462789
Mariana Siniscalchi, Nicolás Gammarano, C. Galup-Montoro, S. Bourdel, F. Silveira
{"title":"Minimum Supply Voltage of 2.45 GHz LC Oscillator in 28 nm FD-SOI Process","authors":"Mariana Siniscalchi, Nicolás Gammarano, C. Galup-Montoro, S. Bourdel, F. Silveira","doi":"10.1109/NEWCAS50681.2021.9462789","DOIUrl":"https://doi.org/10.1109/NEWCAS50681.2021.9462789","url":null,"abstract":"The minimum supply voltage limit is studied in the case of a 2.45 GHz LC cross-coupled oscillator, in a 28 nm FD-SOI technology. An approach with simple equations aided with look up tables is used to obtain a theoretical prediction of the minimum voltage and current required for operation. The look up tables are loaded with all the transistor parameters of interest, which are extracted by means of DC simulations. The prediction is in good agreement with the simulation results, as long as the transition frequency of the transistors is at least 10 times the oscillation frequency. A feasible supply voltage for this circuit topology, oscillation frequency and technology is shown to be 37 mV. Depending on the back-plane voltage value and the inductor selected, the supply voltage reduction is limited by either the parasitic capacitances or the intrinsic gain of the transistors. Equations are provided to aid the designer in the selection of all of the design parameters to achieve the lowest possible supply voltage and lowest possible current.","PeriodicalId":373745,"journal":{"name":"2021 19th IEEE International New Circuits and Systems Conference (NEWCAS)","volume":"94 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127330640","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
An Energy Efficient and Scalable Node Architecture for Sensor Network 一种面向传感器网络的节能可扩展节点架构
2021 19th IEEE International New Circuits and Systems Conference (NEWCAS) Pub Date : 2021-06-13 DOI: 10.1109/NEWCAS50681.2021.9462760
Yassine Faize, J. Crenne, N. Hanusse, C. Jégo
{"title":"An Energy Efficient and Scalable Node Architecture for Sensor Network","authors":"Yassine Faize, J. Crenne, N. Hanusse, C. Jégo","doi":"10.1109/NEWCAS50681.2021.9462760","DOIUrl":"https://doi.org/10.1109/NEWCAS50681.2021.9462760","url":null,"abstract":"Smart campuses are a real challenge to reduce energy consumption and carbon footprint. Wireless sensor networks are useful for monitoring building consumption and activities. To ease the design of autonomous and wireless sensors for those purposes, this paper presents a methodology that includes a sensor node architectural model associated with an energy consumption model. The presented node architecture includes a solar energy harvesting technique and a Wake-up radio to increase autonomy while keeping a sufficient quality of service. Nodes have been deployed in University rooms and real experiments have been investigated to validate the proposed methodology. The consumption model shows an estimation error of less than 2% when compared to real case experiments. By extrapolating the results of nodes based on the proposed architecture model, the in-field experiment announces a virtually unlimited lifetime.","PeriodicalId":373745,"journal":{"name":"2021 19th IEEE International New Circuits and Systems Conference (NEWCAS)","volume":"74 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127339614","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 20 μW, 50 mV, Fully-Integrated Cross-Coupled Oscillator for On-Body IoT Applications 一个20 μW, 50 mV，全集成交叉耦合振荡器，用于体上物联网应用
2021 19th IEEE International New Circuits and Systems Conference (NEWCAS) Pub Date : 2021-06-13 DOI: 10.1109/NEWCAS50681.2021.9462769
M. B. Machado, R. L. Radin, M. C. Schneider, C. Galup-Montoro
{"title":"A 20 μW, 50 mV, Fully-Integrated Cross-Coupled Oscillator for On-Body IoT Applications","authors":"M. B. Machado, R. L. Radin, M. C. Schneider, C. Galup-Montoro","doi":"10.1109/NEWCAS50681.2021.9462769","DOIUrl":"https://doi.org/10.1109/NEWCAS50681.2021.9462769","url":null,"abstract":"An ultra-low-power oscillator for on-body-devices wireless transmitters is designed and implemented in 130 nm CMOS process. This paper explores the reduction of the supply voltage to reduce the power consumption of LC oscillators used in transmitters, complying with imperative requirements of low power dissipation for connected on-body and implanted medical devices. The limits of the voltage supply reduction on the performance of the LC oscillators are researched and important parameters such as phase noise, power consumption and the typical figure of merit are inspected. Measurements results show that the oscillator achieves -88 dBc/Hz of phase noise for a 50-mV supply voltage and -111 dBc/Hz for 200 mV at Df = 200 kHz, while consuming only 20 mW and 118 mW of DC power, respectively.","PeriodicalId":373745,"journal":{"name":"2021 19th IEEE International New Circuits and Systems Conference (NEWCAS)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121268184","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A High-Accuracy and Energy-Efficient CORDIC based Izhikevich Neuron 基于CORDIC的高精度节能Izhikevich神经元
2021 19th IEEE International New Circuits and Systems Conference (NEWCAS) Pub Date : 2021-06-13 DOI: 10.1109/NEWCAS50681.2021.9462786
Zixuan Peng, Jipeng Wang, Yi Zhan, Run Min, Guoyi Yu, Jianwen Luo, Kwen-Siong Chong, Chao Wang
{"title":"A High-Accuracy and Energy-Efficient CORDIC based Izhikevich Neuron","authors":"Zixuan Peng, Jipeng Wang, Yi Zhan, Run Min, Guoyi Yu, Jianwen Luo, Kwen-Siong Chong, Chao Wang","doi":"10.1109/NEWCAS50681.2021.9462786","DOIUrl":"https://doi.org/10.1109/NEWCAS50681.2021.9462786","url":null,"abstract":"Efficient hardware design of biological neuron models is an essential issue in neuromorphic computation research. This paper presents a high-accuracy and energy-efficient hardware design of Izhikevich neuron, in which a fast-convergence COordinate Rotation DIgital Computer (CORDIC) operating in linear system is proposed to calculate square function. A CORDIC error model is also proposed to analyze the error propagation and study the accuracy improvement in the Izhikevich neuron design. Utilizing the fast CORDIC instead of conventional CORDIC, redundant iterations and associated computation are removed, which contributes to both smaller errors and higher efficiency of square calculation. Hence, the proposed fast CORDIC based Izhikevich neuron exhibits higher accuracy and energy efficiency than the conventional CORDIC based design. The FPGA implementation results show that the proposed Izhikevich neuron design achieves 24.2% faster in neuron potential update, 40.7% error reduction, and 45.6% energy-efficiency improvement over the state-of-the-art method, respectively.","PeriodicalId":373745,"journal":{"name":"2021 19th IEEE International New Circuits and Systems Conference (NEWCAS)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132609430","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
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