{"title":"Analytical Modeling of Power Supply Induced Jitter in CMOS Inverters due to Periodic Fluctuations","authors":"Puneet Arora, J. N. Tripathi, H. Shrimali","doi":"10.1109/NEWCAS50681.2021.9462738","DOIUrl":"https://doi.org/10.1109/NEWCAS50681.2021.9462738","url":null,"abstract":"This paper presents an analytical approach to evaluate jitter in the CMOS inverters caused by the periodic fluctuations of the power supply. A closed-form equation of time interval error (TIE) is derived that uses device model parameters to calculate it. In order to derive the output expression for an inverter for various regions of operation which appears during the transition edges, a power series expansion method is used. For the purpose of validation, a 40 nm Ultra Low Power (ULP) commercial technology of TSMC is used with VDD of 1.2 V. The results obtained from the proposed analytical model are verified by comparing them with the simulation results obtained from a standard electronic design automation (EDA) tool, demonstrating an accurate modeling of jitter.","PeriodicalId":373745,"journal":{"name":"2021 19th IEEE International New Circuits and Systems Conference (NEWCAS)","volume":"120 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122331440","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Dynamic Fault Tree Analysis and Risk Mitigation Strategies of Data Communication System via Statistical Model Checking","authors":"Ashkan Samadi, Marwan Ammar, O. Mohamed","doi":"10.1109/NEWCAS50681.2021.9462743","DOIUrl":"https://doi.org/10.1109/NEWCAS50681.2021.9462743","url":null,"abstract":"Fault Tree Analysis (FTA) is a widely used technique to assess the reliability of safety-critical systems. The conventional FTA approaches are based on simulation and often require extensive computing capabilities. In this paper, a model checking based technique is proposed to examine the probability of safety-critical systems failure. The proposed approach uses the advantages of both dynamic FTA and statistical model checking (SMC). In order to illustrate our proposed approach, the sources of failure in Data Communication System (DCS) are analyzed. After detecting the critical causes of system failure, several redundant architectures based on Triple Modular Redundancy (TMR) are investigated to assess their capabilities of risk mitigation.","PeriodicalId":373745,"journal":{"name":"2021 19th IEEE International New Circuits and Systems Conference (NEWCAS)","volume":"109 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124856053","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A 250-600 MHz Ring Oscillator-Based Phase-Locked Loop for Implantable Wireline Applications, Using 1.0 V Supply in 180 nm CMOS","authors":"Taufiq Ahmed, Naila Tasneem, Ross M. Walker","doi":"10.1109/NEWCAS50681.2021.9462757","DOIUrl":"https://doi.org/10.1109/NEWCAS50681.2021.9462757","url":null,"abstract":"This article introduces a low power frequency synthesizer designed for high-speed implantable wireline applications, based on the integer-N phase-locked loop (PLL) architecture. The PLL is designed in a standard 180 nm CMOS process and post-layout simulation results are presented. It provides 8 outputs from 4 delay cells, precisely at 45° apart to facilitate the required parallelism in the transmitter’s datapath. The ring oscillator is based on interpolating inverter delay cells to create the precise phase difference. The design works between 250 MHz to 600 MHz, provides tuning options for robust operation over process variations, draws 2.0-2.6 mW across corners from ±500 mV split supplies, and exhibits a typical phase noise of -83 dBc/Hz at 1 MHz of frequency offset. The typical RMS jitter over 10,000 cycles is 28 ps for a 600 MHz clock. The featured clock synthesizer provides a broader range of operational frequency compared to previous works on multi-phase ring oscillator-based clock synthesizers by utilizing a combination of programmable charge pump current, capacitive load, and tunable biasing. This frequency synthesizer is suitable for power-constrained system-on-chip applications that benefit from strong analog capabilities, such as implantable devices that need transceivers operating in the ISM band.","PeriodicalId":373745,"journal":{"name":"2021 19th IEEE International New Circuits and Systems Conference (NEWCAS)","volume":"52 4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130521708","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A. Boulmirat, J. González-Jiménez, C. Jany, A. Siligaris
{"title":"A High-Order-N Frequency-Multiplier Using Pulsed Oscillator: Modeling and Optimization","authors":"A. Boulmirat, J. González-Jiménez, C. Jany, A. Siligaris","doi":"10.1109/NEWCAS50681.2021.9462793","DOIUrl":"https://doi.org/10.1109/NEWCAS50681.2021.9462793","url":null,"abstract":"This work focusses on the modeling of the Phase Noise (PhN) through the building blocks of a high-order-N frequency multiplication circuit that uses Pulsed injection Locking Oscillator (P-OSC). The proposed analytical expressions allow predicting the transformation of PhN through different blocks of the frequency multiplier. To cope with the inherent nonlinear characteristics of frequency multiplication circuits, simplified nonlinear equivalent circuits (NEC) are used to loosen the time and memory constraints of the numerical simulations. The analytical results show good agreements with Harmonic Balance simulations of NEC. This work helps determining the circuit key parameters controlling Phase Noise and output integrated RMS Jitter for optimization purposes.","PeriodicalId":373745,"journal":{"name":"2021 19th IEEE International New Circuits and Systems Conference (NEWCAS)","volume":"2016 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127420601","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Design of Fast-Settling 40-dB VGA for Closed-loop Current Monitoring System","authors":"E. Azab, Tarek Eldahrawy, Y. Hegazy, K. Hofmann","doi":"10.1109/NEWCAS50681.2021.9462748","DOIUrl":"https://doi.org/10.1109/NEWCAS50681.2021.9462748","url":null,"abstract":"In this paper, a fast-settling Variable Gain Amplifier (VGA) with 40-dB linear-in-decibel gain tuning range is proposed. The VGA is used in a closed-loop current monitoring system and is designed using two cascaded gain cells. The first cell is responsible for the VGA tuning via voltage-to-current control circuit and external resistor with gain range of ±20dB. The second cell’s gain is fixed at 20dB; it is used to stabilize the VGA after adding the common-mode feedback circuit. The VGA is designed using 0.18pm XFAB SOI Technology. Circuit simulations showed that the VGA settling time is 34ns. The VGA’s HD3 is at −73.26dB and its OIP3 of −60dB at maximum gain setting. Comparison with previous work shows that the proposed VGA is faster and has better linearity.","PeriodicalId":373745,"journal":{"name":"2021 19th IEEE International New Circuits and Systems Conference (NEWCAS)","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121588189","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Ahmad M. Jaradat, K. Elgammal, M. K. Özdemir, H. Arslan
{"title":"Identification of The Number of Wireless Channel Taps Using Deep Neural Networks","authors":"Ahmad M. Jaradat, K. Elgammal, M. K. Özdemir, H. Arslan","doi":"10.1109/NEWCAS50681.2021.9462770","DOIUrl":"https://doi.org/10.1109/NEWCAS50681.2021.9462770","url":null,"abstract":"In wireless communication systems, identifying the number of channel taps offers an enhanced estimation of the channel impulse response (CIR). In this work, efficient identification of the number of wireless channel taps has been achieved via deep neural networks (DNNs), where we modified an existing DNN and analyzed its convergence performance using only the transmitted and received signals of a wireless system. The displayed results demonstrate that the adopted DNN accomplishes superior performance in identifying the number of channel taps, as compared to an existing algorithm called Spectrum Weighted Identification of Signal Sources (SWISS).","PeriodicalId":373745,"journal":{"name":"2021 19th IEEE International New Circuits and Systems Conference (NEWCAS)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-10-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121293964","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}