A 250-600 MHz Ring Oscillator-Based Phase-Locked Loop for Implantable Wireline Applications, Using 1.0 V Supply in 180 nm CMOS

This article introduces a low power frequency synthesizer designed for high-speed implantable wireline applications, based on the integer-N phase-locked loop (PLL) architecture. The PLL is designed in a standard 180 nm CMOS process and post-layout simulation results are presented. It provides 8 outputs from 4 delay cells, precisely at 45° apart to facilitate the required parallelism in the transmitter’s datapath. The ring oscillator is based on interpolating inverter delay cells to create the precise phase difference. The design works between 250 MHz to 600 MHz, provides tuning options for robust operation over process variations, draws 2.0-2.6 mW across corners from ±500 mV split supplies, and exhibits a typical phase noise of -83 dBc/Hz at 1 MHz of frequency offset. The typical RMS jitter over 10,000 cycles is 28 ps for a 600 MHz clock. The featured clock synthesizer provides a broader range of operational frequency compared to previous works on multi-phase ring oscillator-based clock synthesizers by utilizing a combination of programmable charge pump current, capacitive load, and tunable biasing. This frequency synthesizer is suitable for power-constrained system-on-chip applications that benefit from strong analog capabilities, such as implantable devices that need transceivers operating in the ISM band.