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2021 19th IEEE International New Circuits and Systems Conference (NEWCAS)最新文献

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A 0.85 V CMOS voltage and current reference using SCCTs 使用scts的0.85 V CMOS电压和电流基准
2021 19th IEEE International New Circuits and Systems Conference (NEWCAS) Pub Date : 2021-06-13 DOI: 10.1109/NEWCAS50681.2021.9462762
Thainann H. P. de Castro, R. Moreno, Dalton Martini Colombo
{"title":"A 0.85 V CMOS voltage and current reference using SCCTs","authors":"Thainann H. P. de Castro, R. Moreno, Dalton Martini Colombo","doi":"10.1109/NEWCAS50681.2021.9462762","DOIUrl":"https://doi.org/10.1109/NEWCAS50681.2021.9462762","url":null,"abstract":"A new circuit topology of a voltage and current reference using self-cascode composite transistors and operating with a minimum supply voltage of 0.85 V is proposed in this work. Using nmos-version and pmos-version self-cascode composite transistors, the reference generates a nominal output voltage and current equal to 540 mV and 1.451 µA with temperature coefficients of 20 ppm/°C and 75 ppm/°C, respectively. The considered temperature range was – 30 °C to 100 °C. The circuit was implemented in a standard 0.18 µm n-well CMOS process, with the layout area of 0.175 mm2 (269 µm × 654 µm), and the supply current consumption of 9.1µA.","PeriodicalId":373745,"journal":{"name":"2021 19th IEEE International New Circuits and Systems Conference (NEWCAS)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115334759","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Battery-Less Face Recognition at the Extreme Edge 极端边缘的无电池面部识别
2021 19th IEEE International New Circuits and Systems Conference (NEWCAS) Pub Date : 2021-06-13 DOI: 10.1109/NEWCAS50681.2021.9462787
Petar Jokic, S. Emery, L. Benini
{"title":"Battery-Less Face Recognition at the Extreme Edge","authors":"Petar Jokic, S. Emery, L. Benini","doi":"10.1109/NEWCAS50681.2021.9462787","DOIUrl":"https://doi.org/10.1109/NEWCAS50681.2021.9462787","url":null,"abstract":"Machine learning-based face recognition systems are commonly used in mobile platforms to assist the camera systems, unlock the device, or analyze the facial expressions. The computational complexity of the underlying algorithms as well as the power consumption of the entire imaging and processing system largely limit the deployment to powerful mobile processing systems with large rechargeable batteries. However, these computer vision capabilities would also be useful in miniaturized low power applications with stringent battery-size limitations. We assess the feasibility of such a computer vision edge processing system on a battery-less credit card-sized demonstrator using an ultra-low power image sensor and a machine learning system-on- chip, achieving self-sustainable operation using solar energy harvesting with a small on-board solar cell. The tested system enables continuous 1 frame-per-second battery-less imaging and face recognition in indoor lighting conditions.","PeriodicalId":373745,"journal":{"name":"2021 19th IEEE International New Circuits and Systems Conference (NEWCAS)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115684870","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Integrated Wideband Millimeter-Wave Bias-Tee – Application to Distributed Amplifier Biasing 集成宽带毫米波偏置电路——在分布式放大器偏置中的应用
2021 19th IEEE International New Circuits and Systems Conference (NEWCAS) Pub Date : 2021-06-13 DOI: 10.1109/NEWCAS50681.2021.9462766
Mohamad El-Chaar, A. A. L. Souza, M. Barragán, F. Podevin, S. Bourdel, J. Arnould
{"title":"Integrated Wideband Millimeter-Wave Bias-Tee – Application to Distributed Amplifier Biasing","authors":"Mohamad El-Chaar, A. A. L. Souza, M. Barragán, F. Podevin, S. Bourdel, J. Arnould","doi":"10.1109/NEWCAS50681.2021.9462766","DOIUrl":"https://doi.org/10.1109/NEWCAS50681.2021.9462766","url":null,"abstract":"A wideband fully-integrated bias-tee well suited for millimeter waves is presented. Compared to conventional bias-tees, where RF-choke is optimized on the basis of its inductance value, here, the proposed RF-choke takes advantage of its low parasitic capacitance as one of the design parameters. While enabling wideband operation, in particular towards lower frequencies, this bias-tee enables ease-of-implementation, robustness against resonance, efficient power delivery to the intended wideband circuit and contributes to circuit area reduction on integrated circuit (IC) implementation. As a proof-of-concept, a wideband CMOS distributed amplifier (DA) with a lower-corner frequency (Flower) of 5 GHz and an upper-corner frequency (Fupper) close to 100 GHz is implemented in STMicroelectronics’ 55-nm technology with the proposed bias-tee connected to its artificial drain line. The implemented bias-tee enabled a bandwidth close to 100 GHz and its RF-choke required a surface area of 82 µm x 82 µm. When integrated along with the DA, the overall chip area remained the same (0.89 mm2). Post-layout simulations showed a DC power overhead (due to inclusion of the on-chip bias-tee) limited to 17% of the DA-only consumption.","PeriodicalId":373745,"journal":{"name":"2021 19th IEEE International New Circuits and Systems Conference (NEWCAS)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123749918","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A Flexible Low-Cost Discrete-Time Wake-up Receiver for LoRaWAN applications 用于LoRaWAN应用的灵活低成本离散时间唤醒接收器
2021 19th IEEE International New Circuits and Systems Conference (NEWCAS) Pub Date : 2021-06-13 DOI: 10.1109/NEWCAS50681.2021.9462784
F. Ferreira, Pietro M. Ferreira, Sandro Binsfeld Ferreira
{"title":"A Flexible Low-Cost Discrete-Time Wake-up Receiver for LoRaWAN applications","authors":"F. Ferreira, Pietro M. Ferreira, Sandro Binsfeld Ferreira","doi":"10.1109/NEWCAS50681.2021.9462784","DOIUrl":"https://doi.org/10.1109/NEWCAS50681.2021.9462784","url":null,"abstract":"This paper presents the design of an innovative discrete-time (DT) wake-up receiver (WuRx) for short-range wireless sensor networks. A switched-capacitor architecture was adopted to implement a digital filter providing some adjustment of the receiver parameters. The inherent aliasing susceptibility of the digital filter is opposed by the current sampler structure as it performs an anti-aliasing function at the input without the typical external bandpass filter solution. The circuit designed for on-off keying (OOK) modulation at 900MHz and a data rate of 100kbps is implemented in 180nm CMOS. Extracted post-layout simulation results show a sensitivity of -70dBm and current consumption of 27.7µA from a 1.2V supply.","PeriodicalId":373745,"journal":{"name":"2021 19th IEEE International New Circuits and Systems Conference (NEWCAS)","volume":"169 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116096660","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Active VSWR Robustness Comparison for Different Phase Combining Topologies 不同相位组合拓扑的主动VSWR鲁棒性比较
2021 19th IEEE International New Circuits and Systems Conference (NEWCAS) Pub Date : 2021-06-13 DOI: 10.1109/NEWCAS50681.2021.9462741
Alexandre Berthier, A. Ghiotto, E. Kerhervé, L. Vogt
{"title":"Active VSWR Robustness Comparison for Different Phase Combining Topologies","authors":"Alexandre Berthier, A. Ghiotto, E. Kerhervé, L. Vogt","doi":"10.1109/NEWCAS50681.2021.9462741","DOIUrl":"https://doi.org/10.1109/NEWCAS50681.2021.9462741","url":null,"abstract":"This paper presents a comparative study on the resilience to load variations brought by combining structures for amplifier topologies. Three out-of-phase four-way combining topologies based on Wilkinson combiners, 90° and 180° hybrid couplers are compared with a conventional in-phase four-way combining topology based on Wilkinson combiners. An experimental evaluation is conducted using a load-pull bench for the characterization of printed circuit board (PCB) demonstrators operating at 2.45 GHz with a VSWR up to 5:1. Measurement results point out the superiority of the out-of-phase combining topologies providing reduced performance variations under load pulling. It is demonstrated that these topologies have a higher resilience to unpredictable load variations, with reduced gain, efficiency, and output power variations. For all the considered out-of-phase combining demonstrators, the gain variation is reduced by more than 1.5 dB at 1 dB compression point compared to the conventional in-phase combining demonstrator.","PeriodicalId":373745,"journal":{"name":"2021 19th IEEE International New Circuits and Systems Conference (NEWCAS)","volume":"132 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129428539","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Exploring flexible and 3D printing technologies for the design of high spatial resolution EM probes 探索柔性3D打印技术用于高空间分辨率电磁探头的设计
2021 19th IEEE International New Circuits and Systems Conference (NEWCAS) Pub Date : 2021-06-13 DOI: 10.1109/NEWCAS50681.2021.9462763
J. Toulemont, F. Mailly, P. Maurine, P. Nouet
{"title":"Exploring flexible and 3D printing technologies for the design of high spatial resolution EM probes","authors":"J. Toulemont, F. Mailly, P. Maurine, P. Nouet","doi":"10.1109/NEWCAS50681.2021.9462763","DOIUrl":"https://doi.org/10.1109/NEWCAS50681.2021.9462763","url":null,"abstract":"Electromagnetic analysis of the field radiated by ICs is a common practice in the field of hardware security, especially for reverse engineering or to disclose cryptographic keys. While surprisingly the scaling of CMOS technologies carries on, it is important to scale down the sensors used to perform such analyses. Within this context, this paper explores the potential of flexible and 3D printing technologies to design low cost, electrically and mechanically robust electromagnetic probes with spatial resolution about 50µm while the standard is currently about 100µm.","PeriodicalId":373745,"journal":{"name":"2021 19th IEEE International New Circuits and Systems Conference (NEWCAS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130556590","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A Wide-range Reconfigurable Deadtime and Delay Element for Optimal-Power Conversion 一种用于最优功率转换的宽范围可重构死区和延时元件
2021 19th IEEE International New Circuits and Systems Conference (NEWCAS) Pub Date : 2021-06-13 DOI: 10.1109/NEWCAS50681.2021.9462732
Mousa Karimi, Mohamed Ali, Ahmad Hassan, M. Sawan, B. Gosselin
{"title":"A Wide-range Reconfigurable Deadtime and Delay Element for Optimal-Power Conversion","authors":"Mousa Karimi, Mohamed Ali, Ahmad Hassan, M. Sawan, B. Gosselin","doi":"10.1109/NEWCAS50681.2021.9462732","DOIUrl":"https://doi.org/10.1109/NEWCAS50681.2021.9462732","url":null,"abstract":"A reconfigurable dead-time circuit intended for optimum power-converters’ operation is presented. The circuit provides a programmable delay element to produce a wide range of dead-time delays for different power conversion’s applications with various loads and input voltages. The circuit utilises two tunable Schmitt triggers, two reconfigurable capacitive banks, and two adjustable-current sources. The post-layout simulation results show that the circuit can produce a wide range of dead-time delays, from 12.8 ns to 952.24 ns, between the control signals of the high and low sides of a power converter. The power consumption of the presented circuit ranges between 323.1 and 89.69 μW, pendant on the selected delay. The presented circuit is implemented in a 0.35-μm AMS CMOS technology where occupies an area of 150 μm×260 μm.","PeriodicalId":373745,"journal":{"name":"2021 19th IEEE International New Circuits and Systems Conference (NEWCAS)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121272694","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Spatial Encoding Techniques in Time-Multiplexed Neural Recording Front-Ends 时间复用神经记录前端的空间编码技术
2021 19th IEEE International New Circuits and Systems Conference (NEWCAS) Pub Date : 2021-06-13 DOI: 10.1109/NEWCAS50681.2021.9462730
Norberto Pérez-Prieto, Á. Rodríguez-Vázquez, M. Delgado-Restituto
{"title":"Spatial Encoding Techniques in Time-Multiplexed Neural Recording Front-Ends","authors":"Norberto Pérez-Prieto, Á. Rodríguez-Vázquez, M. Delgado-Restituto","doi":"10.1109/NEWCAS50681.2021.9462730","DOIUrl":"https://doi.org/10.1109/NEWCAS50681.2021.9462730","url":null,"abstract":"This paper reviews two spatial encoding techniques for time-multiplexed recording front-ends. These techniques use bipolar and monopolar recordings, respectively, and are aimed to compress neural data taking advantage of the large spatial correlation of LFPs/ECoGs measured from nearby electrodes. The pros and cons of both architectures are analyzed and demonstrated with experimental results from a 32-channel time-multiplexed spatially-encoded neural front-end designed in 0.18 μm technology.","PeriodicalId":373745,"journal":{"name":"2021 19th IEEE International New Circuits and Systems Conference (NEWCAS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128193977","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Optimised Model for Piezoelectric Energy Harvesting Circuits Design 压电能量收集电路的优化模型设计
2021 19th IEEE International New Circuits and Systems Conference (NEWCAS) Pub Date : 2021-06-13 DOI: 10.1109/NEWCAS50681.2021.9462792
Lakhdar Mamouri, V. Frick, T. Mesbahi, Liana Wassouf, E. Jamshidpour
{"title":"Optimised Model for Piezoelectric Energy Harvesting Circuits Design","authors":"Lakhdar Mamouri, V. Frick, T. Mesbahi, Liana Wassouf, E. Jamshidpour","doi":"10.1109/NEWCAS50681.2021.9462792","DOIUrl":"https://doi.org/10.1109/NEWCAS50681.2021.9462792","url":null,"abstract":"This paper presents an optimised model dedicated to design integrated systems for piezoelectric energy harvesting. Such systems implement a Full Active Rectifier (FAR) circuit whose efficiency depends on the architecture and switching strategy. In order to replace heavy transistor-level simulations, the proposed highly-configurable Matlab-Simulink® model offers the possibility to study the behaviour and assess the performance of any operation mode. The comparisons between simulations and experimental results performed on a CMOS integrated prototype of our FAR confirm the reliability and robustness of our model. The model thus enables large time scale system-level transient analysis with low computational resources and simulation time.","PeriodicalId":373745,"journal":{"name":"2021 19th IEEE International New Circuits and Systems Conference (NEWCAS)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131956379","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A Wideband RF Receiver Using a Harmonic Rejection N-path Notch Filter for 5G Applications 5G应用中使用谐波抑制n路陷波滤波器的宽带射频接收机
2021 19th IEEE International New Circuits and Systems Conference (NEWCAS) Pub Date : 2021-06-13 DOI: 10.1109/NEWCAS50681.2021.9462734
Nakisa Shams, F. Nabki
{"title":"A Wideband RF Receiver Using a Harmonic Rejection N-path Notch Filter for 5G Applications","authors":"Nakisa Shams, F. Nabki","doi":"10.1109/NEWCAS50681.2021.9462734","DOIUrl":"https://doi.org/10.1109/NEWCAS50681.2021.9462734","url":null,"abstract":"A wideband RF receiver using a harmonic-rejection (HR) N-path notch switching filter with resistive coefficients is presented. It provides harmonic blocker suppression at the input of the RF front-end. The HR notch switching system with resistive coefficients in parallel with the LNA allows for the third harmonic of the switching frequency to be selected. Thus, the input clock frequency of the multi-phase local oscillator (LO) generator and its dynamic power consumption are reduced by a factor of three. The proposed receiver features tunable filtering and high attenuation at the 1st- and 2nd-order LO harmonics at the RF front-end input, improving the harmonic blocker tolerance. The 3.6 −7.2 GHz receiver is implemented in a 65 nm CMOS process. Post-layout simulation results show that the receiver achieves a higher than 57 dB and 63 dB harmonic-rejection ratio at the 1st and 2nd LO harmonics, respectively. The receiver shows a noise figure (NF) of 5.5 dB at a 80 MHz baseband frequency for a 6 GHz RF signal, with a power consumption of 9.8 mW including LO current.","PeriodicalId":373745,"journal":{"name":"2021 19th IEEE International New Circuits and Systems Conference (NEWCAS)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131235156","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
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