F. Ferreira, Pietro M. Ferreira, Sandro Binsfeld Ferreira
{"title":"用于LoRaWAN应用的灵活低成本离散时间唤醒接收器","authors":"F. Ferreira, Pietro M. Ferreira, Sandro Binsfeld Ferreira","doi":"10.1109/NEWCAS50681.2021.9462784","DOIUrl":null,"url":null,"abstract":"This paper presents the design of an innovative discrete-time (DT) wake-up receiver (WuRx) for short-range wireless sensor networks. A switched-capacitor architecture was adopted to implement a digital filter providing some adjustment of the receiver parameters. The inherent aliasing susceptibility of the digital filter is opposed by the current sampler structure as it performs an anti-aliasing function at the input without the typical external bandpass filter solution. The circuit designed for on-off keying (OOK) modulation at 900MHz and a data rate of 100kbps is implemented in 180nm CMOS. Extracted post-layout simulation results show a sensitivity of -70dBm and current consumption of 27.7µA from a 1.2V supply.","PeriodicalId":373745,"journal":{"name":"2021 19th IEEE International New Circuits and Systems Conference (NEWCAS)","volume":"169 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2021-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"A Flexible Low-Cost Discrete-Time Wake-up Receiver for LoRaWAN applications\",\"authors\":\"F. Ferreira, Pietro M. Ferreira, Sandro Binsfeld Ferreira\",\"doi\":\"10.1109/NEWCAS50681.2021.9462784\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents the design of an innovative discrete-time (DT) wake-up receiver (WuRx) for short-range wireless sensor networks. A switched-capacitor architecture was adopted to implement a digital filter providing some adjustment of the receiver parameters. The inherent aliasing susceptibility of the digital filter is opposed by the current sampler structure as it performs an anti-aliasing function at the input without the typical external bandpass filter solution. The circuit designed for on-off keying (OOK) modulation at 900MHz and a data rate of 100kbps is implemented in 180nm CMOS. Extracted post-layout simulation results show a sensitivity of -70dBm and current consumption of 27.7µA from a 1.2V supply.\",\"PeriodicalId\":373745,\"journal\":{\"name\":\"2021 19th IEEE International New Circuits and Systems Conference (NEWCAS)\",\"volume\":\"169 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2021-06-13\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2021 19th IEEE International New Circuits and Systems Conference (NEWCAS)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/NEWCAS50681.2021.9462784\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2021 19th IEEE International New Circuits and Systems Conference (NEWCAS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/NEWCAS50681.2021.9462784","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A Flexible Low-Cost Discrete-Time Wake-up Receiver for LoRaWAN applications
This paper presents the design of an innovative discrete-time (DT) wake-up receiver (WuRx) for short-range wireless sensor networks. A switched-capacitor architecture was adopted to implement a digital filter providing some adjustment of the receiver parameters. The inherent aliasing susceptibility of the digital filter is opposed by the current sampler structure as it performs an anti-aliasing function at the input without the typical external bandpass filter solution. The circuit designed for on-off keying (OOK) modulation at 900MHz and a data rate of 100kbps is implemented in 180nm CMOS. Extracted post-layout simulation results show a sensitivity of -70dBm and current consumption of 27.7µA from a 1.2V supply.