{"title":"5G应用中使用谐波抑制n路陷波滤波器的宽带射频接收机","authors":"Nakisa Shams, F. Nabki","doi":"10.1109/NEWCAS50681.2021.9462734","DOIUrl":null,"url":null,"abstract":"A wideband RF receiver using a harmonic-rejection (HR) N-path notch switching filter with resistive coefficients is presented. It provides harmonic blocker suppression at the input of the RF front-end. The HR notch switching system with resistive coefficients in parallel with the LNA allows for the third harmonic of the switching frequency to be selected. Thus, the input clock frequency of the multi-phase local oscillator (LO) generator and its dynamic power consumption are reduced by a factor of three. The proposed receiver features tunable filtering and high attenuation at the 1st- and 2nd-order LO harmonics at the RF front-end input, improving the harmonic blocker tolerance. The 3.6 −7.2 GHz receiver is implemented in a 65 nm CMOS process. Post-layout simulation results show that the receiver achieves a higher than 57 dB and 63 dB harmonic-rejection ratio at the 1st and 2nd LO harmonics, respectively. The receiver shows a noise figure (NF) of 5.5 dB at a 80 MHz baseband frequency for a 6 GHz RF signal, with a power consumption of 9.8 mW including LO current.","PeriodicalId":373745,"journal":{"name":"2021 19th IEEE International New Circuits and Systems Conference (NEWCAS)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2021-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"A Wideband RF Receiver Using a Harmonic Rejection N-path Notch Filter for 5G Applications\",\"authors\":\"Nakisa Shams, F. Nabki\",\"doi\":\"10.1109/NEWCAS50681.2021.9462734\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A wideband RF receiver using a harmonic-rejection (HR) N-path notch switching filter with resistive coefficients is presented. It provides harmonic blocker suppression at the input of the RF front-end. The HR notch switching system with resistive coefficients in parallel with the LNA allows for the third harmonic of the switching frequency to be selected. Thus, the input clock frequency of the multi-phase local oscillator (LO) generator and its dynamic power consumption are reduced by a factor of three. The proposed receiver features tunable filtering and high attenuation at the 1st- and 2nd-order LO harmonics at the RF front-end input, improving the harmonic blocker tolerance. The 3.6 −7.2 GHz receiver is implemented in a 65 nm CMOS process. Post-layout simulation results show that the receiver achieves a higher than 57 dB and 63 dB harmonic-rejection ratio at the 1st and 2nd LO harmonics, respectively. The receiver shows a noise figure (NF) of 5.5 dB at a 80 MHz baseband frequency for a 6 GHz RF signal, with a power consumption of 9.8 mW including LO current.\",\"PeriodicalId\":373745,\"journal\":{\"name\":\"2021 19th IEEE International New Circuits and Systems Conference (NEWCAS)\",\"volume\":\"9 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2021-06-13\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2021 19th IEEE International New Circuits and Systems Conference (NEWCAS)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/NEWCAS50681.2021.9462734\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2021 19th IEEE International New Circuits and Systems Conference (NEWCAS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/NEWCAS50681.2021.9462734","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A Wideband RF Receiver Using a Harmonic Rejection N-path Notch Filter for 5G Applications
A wideband RF receiver using a harmonic-rejection (HR) N-path notch switching filter with resistive coefficients is presented. It provides harmonic blocker suppression at the input of the RF front-end. The HR notch switching system with resistive coefficients in parallel with the LNA allows for the third harmonic of the switching frequency to be selected. Thus, the input clock frequency of the multi-phase local oscillator (LO) generator and its dynamic power consumption are reduced by a factor of three. The proposed receiver features tunable filtering and high attenuation at the 1st- and 2nd-order LO harmonics at the RF front-end input, improving the harmonic blocker tolerance. The 3.6 −7.2 GHz receiver is implemented in a 65 nm CMOS process. Post-layout simulation results show that the receiver achieves a higher than 57 dB and 63 dB harmonic-rejection ratio at the 1st and 2nd LO harmonics, respectively. The receiver shows a noise figure (NF) of 5.5 dB at a 80 MHz baseband frequency for a 6 GHz RF signal, with a power consumption of 9.8 mW including LO current.