Analytical Modeling of Power Supply Induced Jitter in CMOS Inverters due to Periodic Fluctuations

This paper presents an analytical approach to evaluate jitter in the CMOS inverters caused by the periodic fluctuations of the power supply. A closed-form equation of time interval error (TIE) is derived that uses device model parameters to calculate it. In order to derive the output expression for an inverter for various regions of operation which appears during the transition edges, a power series expansion method is used. For the purpose of validation, a 40 nm Ultra Low Power (ULP) commercial technology of TSMC is used with VDD of 1.2 V. The results obtained from the proposed analytical model are verified by comparing them with the simulation results obtained from a standard electronic design automation (EDA) tool, demonstrating an accurate modeling of jitter.