超低电压低于100 mV Vdd CMOS

2021 19th IEEE International New Circuits and Systems Conference (NEWCAS) Pub Date : 2021-06-13 DOI:10.1109/NEWCAS50681.2021.9462735

S. Aunet

{"title":"超低电压低于100 mV Vdd CMOS","authors":"S. Aunet","doi":"10.1109/NEWCAS50681.2021.9462735","DOIUrl":null,"url":null,"abstract":"Logic and memory proven in silicon, operating at sub-100 mV Vdds are discussed. Static CMOS is likely to be augmented with Schmitt-trigger based solutions, especially for memories that should operate at Vdds below 100 mV.","PeriodicalId":373745,"journal":{"name":"2021 19th IEEE International New Circuits and Systems Conference (NEWCAS)","volume":"71 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2021-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"Ultra Low Voltage Sub-100 mV Vdd CMOS\",\"authors\":\"S. Aunet\",\"doi\":\"10.1109/NEWCAS50681.2021.9462735\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Logic and memory proven in silicon, operating at sub-100 mV Vdds are discussed. Static CMOS is likely to be augmented with Schmitt-trigger based solutions, especially for memories that should operate at Vdds below 100 mV.\",\"PeriodicalId\":373745,\"journal\":{\"name\":\"2021 19th IEEE International New Circuits and Systems Conference (NEWCAS)\",\"volume\":\"71 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2021-06-13\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2021 19th IEEE International New Circuits and Systems Conference (NEWCAS)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/NEWCAS50681.2021.9462735\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2021 19th IEEE International New Circuits and Systems Conference (NEWCAS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/NEWCAS50681.2021.9462735","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 1

摘要

讨论了在低于100 mV的vdd下工作的逻辑和存储器。静态CMOS可能会与基于施密特触发的解决方案相结合，特别是对于应该在低于100 mV的vdd下工作的存储器。

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Ultra Low Voltage Sub-100 mV Vdd CMOS

Logic and memory proven in silicon, operating at sub-100 mV Vdds are discussed. Static CMOS is likely to be augmented with Schmitt-trigger based solutions, especially for memories that should operate at Vdds below 100 mV.

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2021 19th IEEE International New Circuits and Systems Conference (NEWCAS)

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