发布求助
文献互助 智能选刊 最新文献

2021 19th IEEE International New Circuits and Systems Conference (NEWCAS)最新文献

筛选
英文 中文
An Energy-Detection Impulse-Radio UWB Receiver 一种能量探测脉冲无线电超宽带接收机
2021 19th IEEE International New Circuits and Systems Conference (NEWCAS) Pub Date : 2021-06-13 DOI: 10.1109/NEWCAS50681.2021.9462782
Patrick Fath, S. Schmickl, Thomas Faseth, H. Pretl
{"title":"An Energy-Detection Impulse-Radio UWB Receiver","authors":"Patrick Fath, S. Schmickl, Thomas Faseth, H. Pretl","doi":"10.1109/NEWCAS50681.2021.9462782","DOIUrl":"https://doi.org/10.1109/NEWCAS50681.2021.9462782","url":null,"abstract":"In this work, the implementation of a 7 GHz non-coherent energy-detection impulse-radio UWB receiver is discussed for a pulse-position modulation scheme. The radio-frequency chain starts with a repeated filter-amplifier structure with 47.2 dB gain and 7.2 dB noise figure. The IR-UWB signal is detected using an envelope detector with 500 MHz bandwidth and two time-interleaved broadband integrator circuits. Synchronization, demodulation, and error correction are carried out in real-time in the digital baseband, implemented in an FPGA. The receiver achieves a typical communication range of 12 m for an indoor scenario using a standard-compliant custom integrated circuit IR-UWB transmitter and a custom protocol, whereby 30 pulse-position encoded symbols are combined into one frame. The frame error rate has been measured at the target application’s frame rate of 256 frame/s and indicates a sensitivity level of −99.1 dBm at a frame error rate of 1 × 10−3.","PeriodicalId":373745,"journal":{"name":"2021 19th IEEE International New Circuits and Systems Conference (NEWCAS)","volume":"189 5","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131992651","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A Low-Noise mm-Wave Injection-Locked Oscillator designed in 65nm Partially Depleted SOI CMOS Technology 采用65nm部分耗尽SOI CMOS技术设计的低噪声毫米波注入锁定振荡器
2021 19th IEEE International New Circuits and Systems Conference (NEWCAS) Pub Date : 2021-06-13 DOI: 10.1109/NEWCAS50681.2021.9462758
Romane Dumont, M. D. Matos, A. Cathelin, Y. Deval
{"title":"A Low-Noise mm-Wave Injection-Locked Oscillator designed in 65nm Partially Depleted SOI CMOS Technology","authors":"Romane Dumont, M. D. Matos, A. Cathelin, Y. Deval","doi":"10.1109/NEWCAS50681.2021.9462758","DOIUrl":"https://doi.org/10.1109/NEWCAS50681.2021.9462758","url":null,"abstract":"A low-phase-noise injection-locked oscillator (ILO) based on a cross-coupled oscillator topology is presented. The prototype ILO was designed and fabricated in a 65-nm Partially Depleted SOI (PD-SOI) CMOS technology from STMicroelectronics. The 27.47 GHz free-running oscillator exhibits a phase noise of –119.23 dBc/Hz at 10-MHz offset, and its robustness to process variations is less than 4 dB. Using a common mode injection, the proposed ILO generates an output frequency at 27.5-GHz when the oscillator is injection-locked by the 5th harmonic of a 5.5 GHz reference. In injection-locked mode, the phase noise performance is then –116.75 dBc/Hz and – 135 dBc/Hz at 1-MHz and 10-MHz offsets, respectively, while solely consuming 2.06 mW from a 1 V supply. The total active area is 0.031 mm2 (excluding I/O pads).","PeriodicalId":373745,"journal":{"name":"2021 19th IEEE International New Circuits and Systems Conference (NEWCAS)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134556658","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Low Power Ultra-Wide Band Pulse Generator based on a Duty-Cycled 2-ASK Emitter 基于占空比2-ASK发射极的低功耗超宽带脉冲发生器
2021 19th IEEE International New Circuits and Systems Conference (NEWCAS) Pub Date : 2021-06-13 DOI: 10.1109/NEWCAS50681.2021.9462739
F. Artemio-Schoulten, A. Mariano, R. Vauché, S. Bourdel, J. Gaubert, N. Dehaese, H. Barthélemy
{"title":"Low Power Ultra-Wide Band Pulse Generator based on a Duty-Cycled 2-ASK Emitter","authors":"F. Artemio-Schoulten, A. Mariano, R. Vauché, S. Bourdel, J. Gaubert, N. Dehaese, H. Barthélemy","doi":"10.1109/NEWCAS50681.2021.9462739","DOIUrl":"https://doi.org/10.1109/NEWCAS50681.2021.9462739","url":null,"abstract":"This paper presents an ultra-wideband pulse generator based on a duty-cycled 2-ASK emitter able to generate OOK and BPSK modulated carriers. This emitter uses a differential architecture which has been designed in FD-SOI 28 nm CMOS technology with a supply voltage of 1.0 V. It presents a fast enough transient response to entirely cover the 3.1-10.6 GHz FCC band. Moreover, it can be quickly turned-on and turned-off which allow 3 ns pulses to be generated and also, low power impulse communications to be implemented. The emitter is built around a wideband Voltage Controlled Oscillator (VCO) which is able to generate at its outputs large oscillations from 1.0 GHz to 13.9 GHz. When the emitter is used as a 3 ns pulse generator centred on 7987 MHz, its energy consumption is 152.7 pJ/pulse, and the static power consumption is 3.83 μW. This leads to a mean power consumption of 5.36 µW (resp. 19.1 µW and 156 µW) for a pulse repetition frequency of 10 kHz (resp. 100 kHz and 1 MHz), which highlights the interest of impulse modulations for low power radio-frequency communications.","PeriodicalId":373745,"journal":{"name":"2021 19th IEEE International New Circuits and Systems Conference (NEWCAS)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132958747","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Compact, Low-Phase Noise Fractional-N PLL for Global Navigation Receiver 一种用于全球导航接收机的紧凑型低相位噪声分数n锁相环
2021 19th IEEE International New Circuits and Systems Conference (NEWCAS) Pub Date : 2021-06-13 DOI: 10.1109/NEWCAS50681.2021.9462747
Ajinkya Kharalkar, Mukul Pancholi, Vijaya Kumar Kanchetla, Aniruddha Khade, S. Khyalia, Syed Hameed, R. Zele
{"title":"A Compact, Low-Phase Noise Fractional-N PLL for Global Navigation Receiver","authors":"Ajinkya Kharalkar, Mukul Pancholi, Vijaya Kumar Kanchetla, Aniruddha Khade, S. Khyalia, Syed Hameed, R. Zele","doi":"10.1109/NEWCAS50681.2021.9462747","DOIUrl":"https://doi.org/10.1109/NEWCAS50681.2021.9462747","url":null,"abstract":"This paper presents a compact, low-phase noise fractional-N phase-locked loop (PLL) for navigation receivers operating in the frequency bands L1, L2, L5, and S (1.1-2.5 GHz). The PLL supports multi-standard navigation receivers for IRNSS, GPS, Galileo, Beidou, and GLONASS. A new PLL architecture using a single LC voltage controlled-oscillator (VCO) is proposed for multiband operation compared to the state of the art receivers using multiple VCOs or PLLs for the multi-band operation. A 3rd order 1-bit Delta-Sigma Modulator (DSM) is used for fractional frequency division. The PLL achieves the best phase noise of -116.2 dBc/Hz at 1 MHz offset in the L5 band. The PLL is integrated into a multi-standard navigation receiver, fabricated in 65 nm CMOS technology. The PLL consumes a power of 15.7 mW from a 1.2 V supply and occupies an area of 0.25 mm2 in the complete receiver.","PeriodicalId":373745,"journal":{"name":"2021 19th IEEE International New Circuits and Systems Conference (NEWCAS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131045781","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Secure Test with RSNs: Seamless Authenticated Extended Confidentiality 使用rsn的安全测试:无缝认证扩展机密性
2021 19th IEEE International New Circuits and Systems Conference (NEWCAS) Pub Date : 2021-06-13 DOI: 10.1109/NEWCAS50681.2021.9462778
P. Maistri, Vincent Reynaud, M. Portolan, R. Leveugle
{"title":"Secure Test with RSNs: Seamless Authenticated Extended Confidentiality","authors":"P. Maistri, Vincent Reynaud, M. Portolan, R. Leveugle","doi":"10.1109/NEWCAS50681.2021.9462778","DOIUrl":"https://doi.org/10.1109/NEWCAS50681.2021.9462778","url":null,"abstract":"The testability of electronic devices is of critical importance and it is often supported by IEEE standards. The presence of test structures, on the other hand, paves the way for malicious attackers to access the circuit and extract confidential knowledge such as secret keys or intellectual property. Removing the access to these structures after manufacturing test may prevent security breaches, but this solution is not definitive and excludes the possibility of advanced uses such as online debugging, diagnosis of designs and on-line updates or monitoring. For this reason, it is important to maintain the test infrastructure but to protect it against threats either external (e.g., attackers) or internal (e.g., hardware trojans). This can be achieved through protocols ensuring authentication added to confidentiality capabilities. In the case of Reconfigurable Scan Networks (RSN - IEEE 1687), some solutions currently exist, but are limited to external threats. In this paper, we review the recent state of the art in the domain, and present a novel solution addressing in a comprehensive and low-cost manner authentication and confidentiality, both inside and outside the device.","PeriodicalId":373745,"journal":{"name":"2021 19th IEEE International New Circuits and Systems Conference (NEWCAS)","volume":"100 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122833449","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Novel Decimation Topology with Improved Jitter Performance for Clock and Data Recovery Systems 改进时钟和数据恢复系统抖动性能的新型抽取拓扑
2021 19th IEEE International New Circuits and Systems Conference (NEWCAS) Pub Date : 2021-06-13 DOI: 10.1109/NEWCAS50681.2021.9462785
Muhamed F. Allam, Ahmed Abdelrahman, H. Omran, S. Ibrahim
{"title":"Novel Decimation Topology with Improved Jitter Performance for Clock and Data Recovery Systems","authors":"Muhamed F. Allam, Ahmed Abdelrahman, H. Omran, S. Ibrahim","doi":"10.1109/NEWCAS50681.2021.9462785","DOIUrl":"https://doi.org/10.1109/NEWCAS50681.2021.9462785","url":null,"abstract":"This paper discusses the effect of the decimation topology on the jitter performance of Bang-Bang phase detector-based digital Clock and Data Recovery (CDR) systems. It compares the jitter performance of the most common decimation topologies for a fixed input jitter power. A new decimation topology is also proposed to help decouple the transferred jitter (JTRAN) and the generated jitter (JGEN) from the CDR jitter tolerance (JTOL). The jitter performance of the newly proposed decimator has been verified with a MATLAB/simulink model of the CDR.","PeriodicalId":373745,"journal":{"name":"2021 19th IEEE International New Circuits and Systems Conference (NEWCAS)","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124817873","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Ku-Band Cascode Balanced SiGe Power Amplifier with High Robustness to Active SWR 高抗有源SWR鲁棒性ku波段级联平衡SiGe功率放大器
2021 19th IEEE International New Circuits and Systems Conference (NEWCAS) Pub Date : 2021-06-13 DOI: 10.1109/NEWCAS50681.2021.9462752
B. Coquillas, E. Kerhervé, E. Itcia, L. Roussel, B. Louis, T. Merlet
{"title":"Ku-Band Cascode Balanced SiGe Power Amplifier with High Robustness to Active SWR","authors":"B. Coquillas, E. Kerhervé, E. Itcia, L. Roussel, B. Louis, T. Merlet","doi":"10.1109/NEWCAS50681.2021.9462752","DOIUrl":"https://doi.org/10.1109/NEWCAS50681.2021.9462752","url":null,"abstract":"This paper presents the first efficient Ku-Band SiGe cascode power amplifier (PA) with a highly robust power combination to the active SWR. Two twisted couplers distribute 70.2um2 emitter area in a balanced architecture to achieve reduced impedance transformation through baluns. As proof of concept, the PA was simulated with the 0.13-um SiGe BiCMOS technology. The post layout simulations show a saturated power (Psat) of 25.6dBm and a peak PAE of 30% at 18GHz and 90°C. With a 2:1 SWR the PAE and Pout drop less than 5.5% and 1.1dBm, respectively.","PeriodicalId":373745,"journal":{"name":"2021 19th IEEE International New Circuits and Systems Conference (NEWCAS)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127703765","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A Thorax-Like Mesh Phantom for Testing Electrical Impedance Tomography System Performance 一种用于测试电阻抗断层成像系统性能的类胸腔网状体
2021 19th IEEE International New Circuits and Systems Conference (NEWCAS) Pub Date : 2021-06-13 DOI: 10.1109/NEWCAS50681.2021.9462740
Yan Wu, Qianyu Guo, Wangzilu Lu, Jiajie Huang, Liang Ying, Mingyi Chen, Yongfu Li
{"title":"A Thorax-Like Mesh Phantom for Testing Electrical Impedance Tomography System Performance","authors":"Yan Wu, Qianyu Guo, Wangzilu Lu, Jiajie Huang, Liang Ying, Mingyi Chen, Yongfu Li","doi":"10.1109/NEWCAS50681.2021.9462740","DOIUrl":"https://doi.org/10.1109/NEWCAS50681.2021.9462740","url":null,"abstract":"Electrical Impedance Tomography (EIT) is a non-invasive and radiation-free clinical imaging technology, which is considered to be an effective substitute for CT and MRI. Assessing the performance of EIT requires a phantom for validation, calibration, and comparison. In this paper, we present a thorax-like mesh phantom that can effectively simulate the distribution of human thorax conductivity and optimize the mesh by reducing the number of resistors and exploring the optimal electrode placement. The proposed optimization methods are verified by Simulation Program with Integrated Circuit Emphasis (SPICE) simulation and Electrical Impedance Tomography and Diffuse Optical Tomography Reconstruction Software (EIDORS) image reconstruction. Experimental results demonstrate that our proposed thorax-like mesh phantom gets a high image correlation coefficient (ICC) of 0.680 with only 313 resistors. Our proposed thorax-like mesh phantom can be used for EIT system validation and further promote the research of EIT system.","PeriodicalId":373745,"journal":{"name":"2021 19th IEEE International New Circuits and Systems Conference (NEWCAS)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132691153","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
An 8 Channel Transceiver ASIC to Interface a CMUT Array 与CMUT阵列接口的8通道收发器ASIC
2021 19th IEEE International New Circuits and Systems Conference (NEWCAS) Pub Date : 2021-06-13 DOI: 10.1109/NEWCAS50681.2021.9462791
Prajith Kumar Poongodan, Oleg Sakolski, F. Vanselow, L. Maurer
{"title":"An 8 Channel Transceiver ASIC to Interface a CMUT Array","authors":"Prajith Kumar Poongodan, Oleg Sakolski, F. Vanselow, L. Maurer","doi":"10.1109/NEWCAS50681.2021.9462791","DOIUrl":"https://doi.org/10.1109/NEWCAS50681.2021.9462791","url":null,"abstract":"This paper presents an 8 channel interface ASIC for a 2D Capacitive Micromachined Ultrasonic Transducer (CMUT) array. We propose a novel interfacing scheme to eliminate the need for a high voltage (HV) external DC biasing. A two-level HV driver circuit switches between two HV levels to produce a 47 V peak to peak output pulse with rise and fall times of 78 ns and 67 ns at 1.8 MHz. A resistive feedback transimpedance amplifier (TIA) with 4 adjustable gain settings that converts a time-varying current input into an output voltage is used in the receive path. The TIA has a measured −3 dB bandwidth of 4 MHz at the gain setting employing a 300 kΩ resistor in the feedback network. The input referred noise current is measured to be $2.6{text{pA}}/sqrt {Hz} $. A pulse-echo measurement on a CMUT sample demonstrates successful transmit-receive operation of the system. The chip is fabricated in a 0.18 µm HV SOI CMOS process with an active area of 6 mm2.","PeriodicalId":373745,"journal":{"name":"2021 19th IEEE International New Circuits and Systems Conference (NEWCAS)","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134380266","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A Noise-Cancelling Harmonic Selection Receiver Using an N-Path Filter for 5G Applications 基于n路滤波器的5G消噪谐波选择接收机
2021 19th IEEE International New Circuits and Systems Conference (NEWCAS) Pub Date : 2021-06-13 DOI: 10.1109/NEWCAS50681.2021.9462772
Nakisa Shams, F. Nabki
{"title":"A Noise-Cancelling Harmonic Selection Receiver Using an N-Path Filter for 5G Applications","authors":"Nakisa Shams, F. Nabki","doi":"10.1109/NEWCAS50681.2021.9462772","DOIUrl":"https://doi.org/10.1109/NEWCAS50681.2021.9462772","url":null,"abstract":"A wideband noise-cancelling harmonic rejection (NC-HR) RF receiver using two separate N-path filter-based down-conversion paths is presented to avoid amplification at harmonic blocker frequencies. The proposed harmonic blocker-tolerant architecture suppresses blockers placed at or around integer multiples of the local oscillator (LO) frequency. Moreover, the differential HR N-path switching system with resistive coefficients used in the main down-conversion path allows for the 3rd harmonic of the LO frequency to be selected, helping to reduce the dynamic power consumption of the multi-phase LO generator by a factor of three. Post-layout simulation results show that the 3.6 −7.2 GHz receiver implemented in a 65 nm CMOS process achieves a harmonic-rejection ratio (HRR) of 56 dB, a noise figure (NF) of less than 2.6 dB at a 130 MHz baseband frequency for a 7.2 GHz RF signal, with a power consumption of 12.6 mW including the LO current.","PeriodicalId":373745,"journal":{"name":"2021 19th IEEE International New Circuits and Systems Conference (NEWCAS)","volume":"77 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130347401","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
首页 上一页 下一页 尾页
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整，为了账户安全，请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
请完成安全验证×
相关产品
×
本文献相关产品
联系我们：info@booksci.cn Book学术提供免费学术资源搜索服务，方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号：604180095
Book学术官方微信