{"title":"A Noise-Cancelling Harmonic Selection Receiver Using an N-Path Filter for 5G Applications","authors":"Nakisa Shams, F. Nabki","doi":"10.1109/NEWCAS50681.2021.9462772","DOIUrl":null,"url":null,"abstract":"A wideband noise-cancelling harmonic rejection (NC-HR) RF receiver using two separate N-path filter-based down-conversion paths is presented to avoid amplification at harmonic blocker frequencies. The proposed harmonic blocker-tolerant architecture suppresses blockers placed at or around integer multiples of the local oscillator (LO) frequency. Moreover, the differential HR N-path switching system with resistive coefficients used in the main down-conversion path allows for the 3rd harmonic of the LO frequency to be selected, helping to reduce the dynamic power consumption of the multi-phase LO generator by a factor of three. Post-layout simulation results show that the 3.6 −7.2 GHz receiver implemented in a 65 nm CMOS process achieves a harmonic-rejection ratio (HRR) of 56 dB, a noise figure (NF) of less than 2.6 dB at a 130 MHz baseband frequency for a 7.2 GHz RF signal, with a power consumption of 12.6 mW including the LO current.","PeriodicalId":373745,"journal":{"name":"2021 19th IEEE International New Circuits and Systems Conference (NEWCAS)","volume":"77 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2021-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2021 19th IEEE International New Circuits and Systems Conference (NEWCAS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/NEWCAS50681.2021.9462772","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
Abstract
A wideband noise-cancelling harmonic rejection (NC-HR) RF receiver using two separate N-path filter-based down-conversion paths is presented to avoid amplification at harmonic blocker frequencies. The proposed harmonic blocker-tolerant architecture suppresses blockers placed at or around integer multiples of the local oscillator (LO) frequency. Moreover, the differential HR N-path switching system with resistive coefficients used in the main down-conversion path allows for the 3rd harmonic of the LO frequency to be selected, helping to reduce the dynamic power consumption of the multi-phase LO generator by a factor of three. Post-layout simulation results show that the 3.6 −7.2 GHz receiver implemented in a 65 nm CMOS process achieves a harmonic-rejection ratio (HRR) of 56 dB, a noise figure (NF) of less than 2.6 dB at a 130 MHz baseband frequency for a 7.2 GHz RF signal, with a power consumption of 12.6 mW including the LO current.