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2021 19th IEEE International New Circuits and Systems Conference (NEWCAS)最新文献

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Low-Distortion Correlated Level Shifting Sample-and-Hold Stage 低失真相关电平漂移采样保持阶段
2021 19th IEEE International New Circuits and Systems Conference (NEWCAS) Pub Date : 2021-06-13 DOI: 10.1109/NEWCAS50681.2021.9462783
A. Pierce, Eashwar Thaigarajan, Rajiv Singh, E. Hancioglu, U. Moon, G. Temes
{"title":"Low-Distortion Correlated Level Shifting Sample-and-Hold Stage","authors":"A. Pierce, Eashwar Thaigarajan, Rajiv Singh, E. Hancioglu, U. Moon, G. Temes","doi":"10.1109/NEWCAS50681.2021.9462783","DOIUrl":"https://doi.org/10.1109/NEWCAS50681.2021.9462783","url":null,"abstract":"Sample-and-hold (S/H) stages are important components of data converters and other analog and mixed-mode systems. Their performance is usually limited by the nonideal effects in the active block used. This paper describes new architectures for S/H stages which are capable of delivering nearly ideal performance, even when a very basic and imperfect amplifier is used. In realistic transistor-level simulations, the proposed schemes indicated large (~40 dB) improvements in the SNDR and SFDR performance.","PeriodicalId":373745,"journal":{"name":"2021 19th IEEE International New Circuits and Systems Conference (NEWCAS)","volume":"88 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124147054","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Foster-based Transient Thermal Analysis of SiP for Thermomechanical Studies 热力学研究中基于foster的SiP瞬态热分析
2021 19th IEEE International New Circuits and Systems Conference (NEWCAS) Pub Date : 2021-06-13 DOI: 10.1109/NEWCAS50681.2021.9462767
Touati Djallel eddine, A. Oukaira, Ahmad Hassan, Y. Savaria, A. Lakhssassi
{"title":"Foster-based Transient Thermal Analysis of SiP for Thermomechanical Studies","authors":"Touati Djallel eddine, A. Oukaira, Ahmad Hassan, Y. Savaria, A. Lakhssassi","doi":"10.1109/NEWCAS50681.2021.9462767","DOIUrl":"https://doi.org/10.1109/NEWCAS50681.2021.9462767","url":null,"abstract":"System in Package (SiP) is widely used to miniaturize electronic systems and increase their level of integration. Since reliability and lifetime estimation depend critically on accuracy of thermal models and temperature of inter-layers that constitute the SiP, a Foster based model is proposed to achieve this purpose. In this model, heat transfer between layers of the system and thermal coupling between dies in vertical and horizontal plane are accurately taken into account. As a proof of concept, detailed 3D modeling of a multichip heterogeneous module is performed with Simulink. This model can be used for real-time temperature prediction. The accuracy of predicted junction and inter-layer temperatures are confirmed by Finite Element Method (FEM) analysis.","PeriodicalId":373745,"journal":{"name":"2021 19th IEEE International New Circuits and Systems Conference (NEWCAS)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130480648","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Polynomial Digital-to-Analogic Converter 多项式数模转换器
2021 19th IEEE International New Circuits and Systems Conference (NEWCAS) Pub Date : 2021-06-13 DOI: 10.1109/NEWCAS50681.2021.9462764
Guilherme A. Mattos, Yuri C. R. Toledo, S. Haddad
{"title":"Polynomial Digital-to-Analogic Converter","authors":"Guilherme A. Mattos, Yuri C. R. Toledo, S. Haddad","doi":"10.1109/NEWCAS50681.2021.9462764","DOIUrl":"https://doi.org/10.1109/NEWCAS50681.2021.9462764","url":null,"abstract":"This work presents a new topology for a digital-to-analog converter (DAC) based on polynomial reconstruction. The proposal is to reconstruct a signal with the information of amplitude, time and exponent. The general idea is to use a reconstruction based on signal morphology using a polynomial approximation method, thus being able to significantly reduce the sample rate of the D/A converter. The system generates four base waves and combining them it is possible to generate any exponent. In this work, 16 exponents spaced in different ways, ranging from 2 to 0.25, were tested. The system result shows an RMS error of less than 636 µV for the sharpest curve. A reconstruction of an ECG signal is performed where there is a reduction in the sampling rate of 95.08% compared to a converter with a linear sampling rate of 2 KS/s.","PeriodicalId":373745,"journal":{"name":"2021 19th IEEE International New Circuits and Systems Conference (NEWCAS)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114882994","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Multi-Scale Modeling and Simulation Flow for Oscillatory Neural Networks for Edge Computing 面向边缘计算的振荡神经网络多尺度建模与仿真流程
2021 19th IEEE International New Circuits and Systems Conference (NEWCAS) Pub Date : 2021-06-13 DOI: 10.1109/NEWCAS50681.2021.9462761
S. Carapezzi, Corentin Delacour, G. Boschetto, E. Corti, Madeleine Abernot, A. Nejim, Thierry Gil, S. Karg, A. Todri
{"title":"Multi-Scale Modeling and Simulation Flow for Oscillatory Neural Networks for Edge Computing","authors":"S. Carapezzi, Corentin Delacour, G. Boschetto, E. Corti, Madeleine Abernot, A. Nejim, Thierry Gil, S. Karg, A. Todri","doi":"10.1109/NEWCAS50681.2021.9462761","DOIUrl":"https://doi.org/10.1109/NEWCAS50681.2021.9462761","url":null,"abstract":"An oscillatory neural network (ONN) is a neuromorphic computing paradigm based on encoding of information into the phases of oscillators. In this paper we present an ONN whose elemental unit, the \"neuron\", is implemented through a beyond-CMOS device based on vanadium dioxide (VO2). Such ONN technology provides ultra-low power solutions for performing pattern recognition tasks, and it is ideally suited for edge computing applications. However, exploring the groundwork of the beyond-CMOS ONN paradigm is mandatory premise for its industry-level exploitation. Such foundation entails the building of a holistic simulation flow from materials and devices to circuits, to allow assessment of ONN performance. In this work we report results of this advanced designing approach with special focus over the VO2 oscillator. This establishes the ground to scale up to evaluate beyond-CMOS ONN functionalities for pattern recognition.","PeriodicalId":373745,"journal":{"name":"2021 19th IEEE International New Circuits and Systems Conference (NEWCAS)","volume":"67 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129729598","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A Low-Power Elliptic Curve Processor for WISP WISP低功耗椭圆曲线处理器
2021 19th IEEE International New Circuits and Systems Conference (NEWCAS) Pub Date : 2021-06-13 DOI: 10.1109/NEWCAS50681.2021.9462796
Igor Mendez Cabana, C. S. Cárdenas
{"title":"A Low-Power Elliptic Curve Processor for WISP","authors":"Igor Mendez Cabana, C. S. Cárdenas","doi":"10.1109/NEWCAS50681.2021.9462796","DOIUrl":"https://doi.org/10.1109/NEWCAS50681.2021.9462796","url":null,"abstract":"The accelerated development of the Internet of Things (IoT) has required new ways of implementing sensor networks. An attractive alternative is to use RFID technology as sensor nodes since it does not need batteries. In this context, WISP, which is a programmable RFID tag, generates wide interest. However, a consideration in low-resource device networks is that they are easy targets for cyber-attackers. This is because they are a vulnerable point in the network due to their resource constraints. This is why this work presents a low-power Elliptic Curve architecture implemented in the Igloo Nano FPGA and which complies with the energy constraints to be used with WISP. The results of this work are very important because show that when implementing the \"NIST-192\" standard at a frequency of 6 MHZ, a power of 4.6 mW and 1.68mJ is achieved.","PeriodicalId":373745,"journal":{"name":"2021 19th IEEE International New Circuits and Systems Conference (NEWCAS)","volume":"88 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127726622","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Design of a Switched-Mode Operational Amplifier Operating With a 0.5V Supply Voltage 工作在0.5V电源电压下的开关模式运算放大器设计
2021 19th IEEE International New Circuits and Systems Conference (NEWCAS) Pub Date : 2021-06-13 DOI: 10.1109/NEWCAS50681.2021.9462733
Jannah Al-Hashimi, K. Abugharbieh
{"title":"Design of a Switched-Mode Operational Amplifier Operating With a 0.5V Supply Voltage","authors":"Jannah Al-Hashimi, K. Abugharbieh","doi":"10.1109/NEWCAS50681.2021.9462733","DOIUrl":"https://doi.org/10.1109/NEWCAS50681.2021.9462733","url":null,"abstract":"This work presents a novel design of a switched-mode operational amplifier (SMOA). It consists of two stages. The first stage is a low supply voltage operational amplifier. It utilizes common mode feedback techniques to eliminate current sources and increase the output voltage swing. The second stage is a pulse width modulator (PWM) which transforms the output signal information from voltage to time domain. This results in increasing the voltage swing and reducing the distortion issues that conventional operational amplifiers suffer from. Multi-phase techniques were employed to attenuate the PWM distortion components and increase linearity. The 10-phase SMOA circuit proposed in this work was implemented and simulated using Hspice circuit simulator. It uses 28nm CMOS technology and operates from a 0.5V supply voltage and a 500MHz PWM frequency. It consumes 1.5mW while achieving a 740mV peak-to-peak differential output voltage swing with -43.9dB total harmonic distortion (THD) and 44.7dB spurious free dynamic range (SFDR) when a 1MHz input frequency is used.","PeriodicalId":373745,"journal":{"name":"2021 19th IEEE International New Circuits and Systems Conference (NEWCAS)","volume":"116 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116297177","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Design of a Power Management Circuit for an Opto-Electro Stimulator 光电刺激器电源管理电路的设计
2021 19th IEEE International New Circuits and Systems Conference (NEWCAS) Pub Date : 2021-06-13 DOI: 10.1109/NEWCAS50681.2021.9462777
Noora Almarri, D. Jiang, A. Demosthenous
{"title":"Design of a Power Management Circuit for an Opto-Electro Stimulator","authors":"Noora Almarri, D. Jiang, A. Demosthenous","doi":"10.1109/NEWCAS50681.2021.9462777","DOIUrl":"https://doi.org/10.1109/NEWCAS50681.2021.9462777","url":null,"abstract":"This paper presents the design of an integrated power management circuit for use in an implantable opto-electro stimulator. It features an active rectifier with pulse width modulation (PWM) regulation to generate a 3.3 V regulated output, and a 3-stage high voltage charge pump (CP) that generates a 12 V output from a 3.3 V input with a 20 MHz, two-phase non-overlapping clock generator. The circuits were designed in a 0.18-µm CMOS technology requiring a chip area of 0.048 mm2. Simulation results show that the regulating rectifier has a voltage conversion efficiency of 94.3% and 92.8% with an ac input magnitude of 3.5 V and 3.6 V, respectively. The peak power transfer efficiency of the regulated 3.3V output voltage is 70.7% with a maximum output power of 30.3 mW. The CP with an overall on-chip capacitance is 60 pF.","PeriodicalId":373745,"journal":{"name":"2021 19th IEEE International New Circuits and Systems Conference (NEWCAS)","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126643866","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Temperature Characterization of a Fully-synthesizable Rail-to-Rail Dynamic Voltage Comparator operating down to 0.15-V : (Invited paper) 全合成轨对轨动态电压比较器的温度特性研究(特邀论文)
2021 19th IEEE International New Circuits and Systems Conference (NEWCAS) Pub Date : 2021-06-13 DOI: 10.1109/NEWCAS50681.2021.9462749
O. Aiello, P. Toledo
{"title":"Temperature Characterization of a Fully-synthesizable Rail-to-Rail Dynamic Voltage Comparator operating down to 0.15-V : (Invited paper)","authors":"O. Aiello, P. Toledo","doi":"10.1109/NEWCAS50681.2021.9462749","DOIUrl":"https://doi.org/10.1109/NEWCAS50681.2021.9462749","url":null,"abstract":"This paper deals with the performance/temperature tradeoff in an ultra-low voltage, ultra-low power rail-to-rail dynamic voltage comparator made solely by digital standard cells. The digital nature of the comparator makes its design technology portable also enabling its operation at very low supply voltages down to deep sub-threshold. In particular, as sub-threshold circuits have a significant temperature dependence, this paper focuses on the comparator performance under different supply voltages and temperatures.Measurements performed on a 180nm testchip show correct operation under rail-to-rail common-mode input at a supply voltage ranging from 0.6V down to 0.15V. Moreover, the measurements under temperature variations of offset, clock-to-output delay, and power in the range from -25 °C to 75 °C show the respective performance trade-offs.","PeriodicalId":373745,"journal":{"name":"2021 19th IEEE International New Circuits and Systems Conference (NEWCAS)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125674177","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Skew-Tent Map Based CMOS Random Number Generator with Chaotic Sampling 基于斜帐篷映射的混沌采样CMOS随机数发生器
2021 19th IEEE International New Circuits and Systems Conference (NEWCAS) Pub Date : 2021-06-13 DOI: 10.1109/NEWCAS50681.2021.9462765
Muhammed Mustafa Kizmaz, Salih Ergün
{"title":"Skew-Tent Map Based CMOS Random Number Generator with Chaotic Sampling","authors":"Muhammed Mustafa Kizmaz, Salih Ergün","doi":"10.1109/NEWCAS50681.2021.9462765","DOIUrl":"https://doi.org/10.1109/NEWCAS50681.2021.9462765","url":null,"abstract":"Random number generators (RNGs) has an extensive application area from cryptography to simulation software. Piecewise linear one-dimensional (PL1D) maps are commonly preferred structures used as the basis of RNGs due to their theoretically proven chaotic behavior and ease of implementation. In this work, a skew-tent map based RNG is designed by using the chaotic sampling method in TSMC 180 nm CMOS process. Simulation data of the designed RNG is validated by the statistical randomness tests of the FIPS-140-2 and NIST 800-22 suites. The proposed RNG has three key features: the generated bitstreams can fulfill the randomness tests without using any post processing methods; the proposed RNG has immunity against external interference thanks to the chaotic sampling method; and higher bitrates (4.8 Mbit/s) can be achieved with relatively low power consumption (9.8 mW). Thus, robust RNG systems can be built for high-speed security applications with low power by using the proposed architecture.","PeriodicalId":373745,"journal":{"name":"2021 19th IEEE International New Circuits and Systems Conference (NEWCAS)","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126026770","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Flicker Noise Analysis on Chopper Amplifier 斩波放大器的闪烁噪声分析
2021 19th IEEE International New Circuits and Systems Conference (NEWCAS) Pub Date : 2021-06-13 DOI: 10.1109/NEWCAS50681.2021.9462742
Tingsen Zhou, Zhuo Gao, Jiajie Huang, Yewangqing Lu, Mingyi Chen, Yongfu Li
{"title":"Flicker Noise Analysis on Chopper Amplifier","authors":"Tingsen Zhou, Zhuo Gao, Jiajie Huang, Yewangqing Lu, Mingyi Chen, Yongfu Li","doi":"10.1109/NEWCAS50681.2021.9462742","DOIUrl":"https://doi.org/10.1109/NEWCAS50681.2021.9462742","url":null,"abstract":"This paper aims to maximize the performance of the chopper amplifier, considering the design trade-off between noise and power consumption. To achieve the goal, we identify and model the various sources of flicker noise in the amplifier and switches using Verilog-AMS language. Then, we build a chopper amplifier circuit and investigate the influences of chopping frequency, the type of switches (N-type switch, N-type switch with dummy, transmission gate, and bootstrapped N-type switch) and its non-idealities on its noise performance. Based on our analytical study with simulation results using the circuit model, we can identify the optimal chopping frequency and use N-type switches to minimize mismatch in parasitic capacitance. Therefore, we can reduce the total input-referred-noise by 4.9× compared with an amplifier without using the chopping technique.","PeriodicalId":373745,"journal":{"name":"2021 19th IEEE International New Circuits and Systems Conference (NEWCAS)","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125833337","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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