2021 19th IEEE International New Circuits and Systems Conference (NEWCAS)最新文献_第3页

Incorporation of Chopping in Continuous Time K-Delta-1-Sigma Modulator 连续时间k - δ -1- σ调制器中斩波的应用

2021 19th IEEE International New Circuits and Systems Conference (NEWCAS) Pub Date : 2021-06-13 DOI: 10.1109/NEWCAS50681.2021.9462794

Sachin P. Namboodiri, R. J. Baker

引用次数: 0

RISC-V Resource-Constrained Cores: A Survey and Energy Comparison RISC-V资源约束核心:调查和能源比较

2021 19th IEEE International New Circuits and Systems Conference (NEWCAS) Pub Date : 2021-06-13 DOI: 10.1109/NEWCAS50681.2021.9462781

Islam Elsadek, E. Tawfik

引用次数: 6

A High Speed Fully Integrated Capacitive Digital Isolation System in 0.35 µm CMOS for Industrial Sensor Interfaces 用于工业传感器接口的0.35µm CMOS高速全集成电容式数字隔离系统

2021 19th IEEE International New Circuits and Systems Conference (NEWCAS) Pub Date : 2021-06-13 DOI: 10.1109/NEWCAS50681.2021.9462788

Isa H. Altoobaji, Mohamed Ali, Ahmad Hassan, Y. Audet, A. Lakhssassi

引用次数: 2

An hybrid approach for high-performance passive 120-GHz phase shifters in BiCMOS technology BiCMOS技术中高性能120 ghz无源移相器的混合方法

2021 19th IEEE International New Circuits and Systems Conference (NEWCAS) Pub Date : 2021-06-13 DOI: 10.1109/NEWCAS50681.2021.9462755

David Ouattara, C. Durand, P. Ferrari, S. Bourdel, F. Paillardet

引用次数: 0

Wideband High-Order All-Pass Delay Circuits 宽带高阶全通延迟电路

2021 19th IEEE International New Circuits and Systems Conference (NEWCAS) Pub Date : 2021-06-13 DOI: 10.1109/NEWCAS50681.2021.9462790

Z. Kabirkhoo, M. Radpour, L. Belostotski

引用次数: 1

Ultra Low-Power 2.5µW CMOS Implementation of a Mixed Analog-Digital Wake-Up System Based on Frequency Analysis 基于频率分析的模数混合唤醒系统的超低功耗2.5µW CMOS实现

2021 19th IEEE International New Circuits and Systems Conference (NEWCAS) Pub Date : 2021-06-13 DOI: 10.1109/NEWCAS50681.2021.9462746

Manon Fourniol, V. Gies, V. Barchasz, E. Kussener, R. Vauché, H. Barthélemy, H. Glotin

{"title":"Ultra Low-Power 2.5µW CMOS Implementation of a Mixed Analog-Digital Wake-Up System Based on Frequency Analysis","authors":"Manon Fourniol, V. Gies, V. Barchasz, E. Kussener, R. Vauché, H. Barthélemy, H. Glotin","doi":"10.1109/NEWCAS50681.2021.9462746","DOIUrl":"https://doi.org/10.1109/NEWCAS50681.2021.9462746","url":null,"abstract":"An ultra low power acoustic wake-up detector based on high frequency signal analysis is presented in this paper. Focused on environmental or military Internet of Things (IoT) applications, it aims at detecting in real time the presence of specific animal species or drones for generating alerts and for triggering power consuming tasks such as high frequency signal recording only when needed.This wake-up detector continuously monitors the presence of specific frequencies in an analog acoustic signal, with a good frequency selectivity and a high frequency range detection capability. It is based on an ultra-low power analog frequency to voltage converter using a current-mirror, analog timers and synchronous comparators.Dedicated to long term stealth environmental or military surveys, a strong emphasis has been put on power consumption reduction in order to reduce batteries constraints. Its power consumption has been reduced to 2.5µW, leading to an autonomy of more than 28 years with a single coin cell CR2032 battery.","PeriodicalId":373745,"journal":{"name":"2021 19th IEEE International New Circuits and Systems Conference (NEWCAS)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114507952","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Highly-Adaptive Mixed-Precision MAC Unit for Smart and Low-Power Edge Computing 用于智能和低功耗边缘计算的高自适应混合精度MAC单元

2021 19th IEEE International New Circuits and Systems Conference (NEWCAS) Pub Date : 2021-06-13 DOI: 10.1109/NEWCAS50681.2021.9462745

Guillaume Devic, M. France-Pillois, Jérémie Salles, G. Sassatelli, A. Gamatie

{"title":"Highly-Adaptive Mixed-Precision MAC Unit for Smart and Low-Power Edge Computing","authors":"Guillaume Devic, M. France-Pillois, Jérémie Salles, G. Sassatelli, A. Gamatie","doi":"10.1109/NEWCAS50681.2021.9462745","DOIUrl":"https://doi.org/10.1109/NEWCAS50681.2021.9462745","url":null,"abstract":"Machine learning algorithms are compute- and memory-intensive. Their execution at the edge on resource-constrained embedded systems is challenging. Data quantization, i.e. data bit-width reduction, contributes to reducing de-facto the memory bandwidth requirement. In order to best exploit this bit-width reduction, a prevailing approach consists of tailored hardware accelerators. Another approach relies on general-purpose compute units with Single Instruction Multiple Data (SIMD) support for reduced data bit-width precision, as in ARM Cortex-M [1] or RISC-V based RI5CY [2] processors. However, such processors only handle a few predefined bit-width ranges, e.g. 8-bit and 16-bit only for the ARM SIMD.This paper proposes a flexible architecture of Multiply-and-Accumulate (MAC) unit allowing asymmetric multiplication for operand sizes in powers of 2, up to 32 bits. The synthesis of this architecture in 28nm FD-SOI technology shows 10% and 25% reduction in area and dynamic power respectively, compared to the RI5CY MAC unit. From the energy-efficiency point of view, up to 50% improvements are achieved.","PeriodicalId":373745,"journal":{"name":"2021 19th IEEE International New Circuits and Systems Conference (NEWCAS)","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121419032","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

FPGA Implementation of Parallel Neurosynaptic Cores for Neuromorphic Architectures 神经形态架构中并行神经突触核的FPGA实现

2021 19th IEEE International New Circuits and Systems Conference (NEWCAS) Pub Date : 2021-06-13 DOI: 10.1109/NEWCAS50681.2021.9462774

Vu Truong-Tuan, Chi Hoang-Phuong, Anh Pham-Tuan, Phuc Pham-Hong, Quang Hieu Dang, Hoang Nguyen-Huy, Minh Nguyen-Duc

{"title":"FPGA Implementation of Parallel Neurosynaptic Cores for Neuromorphic Architectures","authors":"Vu Truong-Tuan, Chi Hoang-Phuong, Anh Pham-Tuan, Phuc Pham-Hong, Quang Hieu Dang, Hoang Nguyen-Huy, Minh Nguyen-Duc","doi":"10.1109/NEWCAS50681.2021.9462774","DOIUrl":"https://doi.org/10.1109/NEWCAS50681.2021.9462774","url":null,"abstract":"Fully digital neuromorphic hardware architectures such as IBM’s TrueNorth [1] and Intel’s Loihi [2] have been developed to mimic biologically inspired spiking neural networks (SNNs). Besides being fabricated by CMOS technology, the neuromorphic architecture can be emulated in FPGA SoCs such as those proposed in the RANC framework [6]. In this paper, we present novel parallel neurosynaptic cores containing neurons working simultaneously. The proposed cores can be used in the TrueNorth-inspired neuromorphic architecture to improve performance as well as power consumption. To validate the functional behaviour of the proposed architecture, we construct a SNN containing five parallel neurosynaptic cores to handle the MNIST handwritten digit dataset. Each core consists of 256 neurons working simultaneously. The proposed SNN is implemented on Xilinx Kintex 7 SoC and is as accurate as the sequential SNN implemented in the RANC framework. The synthesised SNN utilises twice the number of LUTs and the same number of flip-flops, IOs and LUTRAM compared to the RANC based SNN. It is 86 times faster in term of images per second being processed. In addition, with the same performance of images per second, our SNN consumes only 36mW of dynamic power which is 22 times lower than the RANC based SNN.","PeriodicalId":373745,"journal":{"name":"2021 19th IEEE International New Circuits and Systems Conference (NEWCAS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129332541","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

Mixed signal compensation of sampling errors in ADCs due to noisy DPLL clock sources 由噪声DPLL时钟源引起的adc采样误差的混合信号补偿

2021 19th IEEE International New Circuits and Systems Conference (NEWCAS) Pub Date : 2021-06-13 DOI: 10.1109/NEWCAS50681.2021.9462737

Hao Zheng, Eric Thompson, J. Hogan, Daniel O’Hare

引用次数: 1

Permanent Laser Fault Injection into the Flash Memory of a Microcontroller 微控制器闪存中的永久激光故障注入

2021 19th IEEE International New Circuits and Systems Conference (NEWCAS) Pub Date : 2021-06-13 DOI: 10.1109/NEWCAS50681.2021.9462773

R. Viera, J. Dutertre, Mathieu Dumont, Pierre-Alain Moëllic

引用次数: 5