FPGA Implementation of Parallel Neurosynaptic Cores for Neuromorphic Architectures

Abstract

Fully digital neuromorphic hardware architectures such as IBM’s TrueNorth [1] and Intel’s Loihi [2] have been developed to mimic biologically inspired spiking neural networks (SNNs). Besides being fabricated by CMOS technology, the neuromorphic architecture can be emulated in FPGA SoCs such as those proposed in the RANC framework [6]. In this paper, we present novel parallel neurosynaptic cores containing neurons working simultaneously. The proposed cores can be used in the TrueNorth-inspired neuromorphic architecture to improve performance as well as power consumption. To validate the functional behaviour of the proposed architecture, we construct a SNN containing five parallel neurosynaptic cores to handle the MNIST handwritten digit dataset. Each core consists of 256 neurons working simultaneously. The proposed SNN is implemented on Xilinx Kintex 7 SoC and is as accurate as the sequential SNN implemented in the RANC framework. The synthesised SNN utilises twice the number of LUTs and the same number of flip-flops, IOs and LUTRAM compared to the RANC based SNN. It is 86 times faster in term of images per second being processed. In addition, with the same performance of images per second, our SNN consumes only 36mW of dynamic power which is 22 times lower than the RANC based SNN.