Incorporation of Chopping in Continuous Time K-Delta-1-Sigma Modulator

Abstract

A chopping technique in a continuous time K-delta-1-sigma modulator (KD1S) is reported in this paper. It is shown that the presence of the inherent path filter in the proposed technique can significantly improve the performance of the modulator by minimizing the aliased quantization noise. Also reported are how the selection of chopping frequency and its relation to sampling frequency and the trade-offs. To support the theory, a first order K-delta-1-sigma topology was designed in a 180nm CMOS process. Simulations are used to illustrate the validity of the results. The modulator works at a sampling frequency of 1 MHz with an oversampling ratio of 256. It consumes an average current of 61.18 µA from 1.8 V supply. The simulation result shows that there is more than 25dB improvement in the Signal-to-Noise Ratio (SNR) of the KD1S, when chopped at the right frequency.