Wideband High-Order All-Pass Delay Circuits

In this work, we present a novel wideband high-order all-pass delay-circuit topology suitable for radio-frequency (RF) applications. The proposed all-pass delay circuit avoids conventional cascading, which degrades bandwidth and increases power consumption. The proposed delay-circuit topology consists of a common-source transistor and a passive impedance network. The delay-circuit order is increased via the passive impedance-network extension. The operation of the all-pass delay circuit is validated through the designs of 4th- and 5th-order all-pass filters in a 22-nm CMOS process. Post-layout simulations of the 4th- and 5th-order delay circuits demonstrate group delays of 60 ps, 90 ps across 17.9 GHz, 18.3 GHz bandwidths while only consuming 1.34 mW, 1.48 mW from a 1 V power supply, respectively.