A High Speed Fully Integrated Capacitive Digital Isolation System in 0.35 µm CMOS for Industrial Sensor Interfaces

This work presents the implementation and simulation of a high speed fully integrated capacitive digital isolation system in 0.35 µm CMOS process. Pulse amplitude modulation scheme was adopted for the proposed design to allow high data rates while maintaining a small integration area compared to the current state-of-art works. The proposed modulation scheme eliminates the need of additional larger on-chip capacitor to support low-frequency operation. Simulation results show that the proposed system supports a wide range of data rates between 50 kbps and 500 Mbps. Moreover, the design shows a propagation delay of only 2 ns from input to output, which allows fast operation.