Mixed signal compensation of sampling errors in ADCs due to noisy DPLL clock sources

Abstract

This paper proposes a method to compensate for sampling errors in ADCs when a noisy digital phase locked-loop (DPLL) is used as the clock source. MATLAB Simulink models are used to create a time domain DPLL model with accurate Phase Noise. Time-to-digital converter (TDC) of the locked DPLL provides an estimate of jitter which is used with an analog differentiator to provide an estimate of the ADC sampling error. An improved compensation allows the ADC effective number of bits at high frequency to be improved from 2 bits to 6 bits.