A. Pierce, Eashwar Thaigarajan, Rajiv Singh, E. Hancioglu, U. Moon, G. Temes
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Sample-and-hold (S/H) stages are important components of data converters and other analog and mixed-mode systems. Their performance is usually limited by the nonideal effects in the active block used. This paper describes new architectures for S/H stages which are capable of delivering nearly ideal performance, even when a very basic and imperfect amplifier is used. In realistic transistor-level simulations, the proposed schemes indicated large (~40 dB) improvements in the SNDR and SFDR performance.
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