2014 7th International Silicon-Germanium Technology and Device Meeting (ISTDM)最新文献

Direct band gap electroluminescence from bulk germanium at room temperature using an asymmetric metal/germanium/metal structure 室温下使用不对称金属/锗/金属结构的体锗直接带隙电致发光

2014 7th International Silicon-Germanium Technology and Device Meeting (ISTDM) Pub Date : 2014-08-11 DOI: 10.1109/ISTDM.2014.6874642

Dong Wang, Sho Kamezawa, K. Yamamoto, H. Nakashima

引用次数: 0

Strain-induced morphological instability and self assembly of tin wires during controlled annealing of Ge0.83Sn0.17 epitaxial film on Ge(001) substrate Ge(001)衬底上Ge0.83Sn0.17外延薄膜控制退火过程中锡丝的形变不稳定性和自组装

2014 7th International Silicon-Germanium Technology and Device Meeting (ISTDM) Pub Date : 2014-06-02 DOI: 10.1109/ISTDM.2014.6874671

Lingzi Li, Wei Wang, E. Tok, Y. Yeo

引用次数: 0

Growth of indium arsenide on silicon-based substrates using molecular beam epitaxy 利用分子束外延在硅基衬底上生长砷化铟

2014 7th International Silicon-Germanium Technology and Device Meeting (ISTDM) Pub Date : 2014-06-02 DOI: 10.1109/ISTDM.2014.6874657

K. Tan, W. Loke, S. Wicaksono, S. Yoon, S. Subramanian, Qian Zhou, Y. Yeo

引用次数: 0

Si CMOS compatible, compliant integration of lattice-mismatched semiconductors on Si(001): Example of fully coherent Ge/Si nanostructures Si CMOS兼容，硅(001)上晶格不匹配半导体的兼容集成:完全相干的Ge/Si纳米结构的例子

2014 7th International Silicon-Germanium Technology and Device Meeting (ISTDM) Pub Date : 2014-06-02 DOI: 10.1109/ISTDM.2014.6874624

F. Montalenti, M. Salvalaglio, A. Marzegalli, P. Zaumseil, G. Capellini, T. Schulli, M. Schubert, Y. Yamamoto, B. Tillack, T. Schroeder

{"title":"Si CMOS compatible, compliant integration of lattice-mismatched semiconductors on Si(001): Example of fully coherent Ge/Si nanostructures","authors":"F. Montalenti, M. Salvalaglio, A. Marzegalli, P. Zaumseil, G. Capellini, T. Schulli, M. Schubert, Y. Yamamoto, B. Tillack, T. Schroeder","doi":"10.1109/ISTDM.2014.6874624","DOIUrl":"https://doi.org/10.1109/ISTDM.2014.6874624","url":null,"abstract":"In this paper, we revisited the so-called \"compliance\" heteroepitaxy concept which was e.g. reported by Hirth and Lothe already in the early sixties. The vision of this concept is to shift the critical thickness for plastic relaxation by defect injection of a growing heteroepitaxial thin film structure on a substrate to infinity. In other words, in case of the Ge/Si heterosystem, defect free Ge heterostructures on Si(001) without threading arm defects in the volume of the Ge film and without misfit dislocations at the Ge/Si heterostructure interface would result. To achieve this goal, the compliance approach is based on a subtle strain partitioning between Ge film and Si substrate so that the increasing mismatch strain is not only absorbed in the epitaxial Ge film but also in part into the Si substrate. As Hirth and Lothe proposed the use of nanometer thick and thus unrealistically thin Si substrates, it was our goal to establish compliant growth for the Ge/Si heterosystem under Si CMOS compatible conditions.","PeriodicalId":371483,"journal":{"name":"2014 7th International Silicon-Germanium Technology and Device Meeting (ISTDM)","volume":"85 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115996028","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Arsenic atomic layer doping in Si using AsH3 用AsH3掺杂硅中的砷原子层

2014 7th International Silicon-Germanium Technology and Device Meeting (ISTDM) Pub Date : 2014-06-02 DOI: 10.1109/ISTDM.2014.6874638

Y. Yamamoto, R. Kurps, Juichi Murota, B. Tillack

引用次数: 3

III–V/Ge CMOS device technologies for future logic LSIs 未来逻辑lsi的III-V /Ge CMOS器件技术

2014 7th International Silicon-Germanium Technology and Device Meeting (ISTDM) Pub Date : 2014-06-02 DOI: 10.1109/ISTDM.2014.6874696

S. Takagi, M. Takenaka

{"title":"III–V/Ge CMOS device technologies for future logic LSIs","authors":"S. Takagi, M. Takenaka","doi":"10.1109/ISTDM.2014.6874696","DOIUrl":"https://doi.org/10.1109/ISTDM.2014.6874696","url":null,"abstract":"CMOS utilizing high mobility Ge/III-V channels on Si substrates is expected to be one of promising devices for high performance and low power logic LSIs in the future [1, 2]. There can be several CMOS structures using III-V/Ge channels, as schematically shown in Fig. 1. Viable CMOS structures using III-V and/or Ge channels are still strongly dependent on coming progress in the device/process/integration technologies of III-V/Ge MOS devices. Here, one of the most important issues for applying to the future technology nodes is suppression of short channel effects, which can be realized by ultrathin body (UTB) channels. Particularly, we would prefer planar UTB/UTBOX-based structures, which can realize further improvement of SCEs by combination with multi-gate structures such as FinFET and Tri-gate/nanowire MOSFETs, as shown in Fig. 2. This scheme allows us to provide static and/or dynamic Vth control through UTBOX by Si substrate doping and back bias under simple structures and fabrication processes. As for Ge-based CMOS, easy integration of GOI/SGOI is possible under the present SOI/sSOI platform. Here, the difficult challenges for realizing high performance logic devices include the III-V/Ge ultrathin body channel formation, the low resistivity S/D formation, the mobility enhancement in such ultrathin body channels and superior MOS gate stacks. Our approach for the channel formation is the wafer bonding and the Ge condensation. Also, metal S/D technologies are regarded as promising for reducing parasitic S/D resistance. In order to maintain high channel mobility, we employ optimized channel design of quantum wells (QW) with MOS interface buffers for III-V channels, and surface orientation and strain engineering for Ge channels. The GeOx-based gate stacks are important for obtaining high mobility Ge MOSFETs with ultrathin EOT.","PeriodicalId":371483,"journal":{"name":"2014 7th International Silicon-Germanium Technology and Device Meeting (ISTDM)","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127621276","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Strained Ge0.96Sn0.04 P-channel MOSFETs with in situ low temperature Si2H6 surface passivation 应变Ge0.96Sn0.04 p沟道mosfet与原位低温Si2H6表面钝化

2014 7th International Silicon-Germanium Technology and Device Meeting (ISTDM) Pub Date : 2014-06-02 DOI: 10.1109/ISTDM.2014.6874637

Yan Liu, Jing Yan, G. Han, Hongjuan Wang, Mingshan Liu, Chunfu Zhang, B. Cheng, Y. Hao

引用次数: 1

Ultralow-temperature catalyst-induced-crystallization of SiGe on plastic for flexible electronics 柔性电子用塑料上SiGe的超低温催化结晶

2014 7th International Silicon-Germanium Technology and Device Meeting (ISTDM) Pub Date : 2014-06-02 DOI: 10.1109/ISTDM.2014.6874633

T. Sadoh, J. Park, M. Kurosawa, M. Miyao

引用次数: 0

Full 3D process/device simulations re-using 2D TCAD knowledge for optimizing N and P-type FinFET transistors 利用2D TCAD知识进行全3D工艺/器件模拟，优化N型和p型FinFET晶体管

2014 7th International Silicon-Germanium Technology and Device Meeting (ISTDM) Pub Date : 2014-06-02 DOI: 10.1109/ISTDM.2014.6874650

F. Benistant, M. Bazizi, L. Jiang, J. H. B. Tng, M. H. J. Goh

引用次数: 1

Epitaxy of light emitting SiGeSn materials using novel precursors 利用新型前驱体的发光SiGeSn材料外延

2014 7th International Silicon-Germanium Technology and Device Meeting (ISTDM) Pub Date : 2014-06-02 DOI: 10.1109/ISTDM.2014.6874700

J. Kouvetakis, J. Menéndez

引用次数: 0