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ICM 2001 Proceedings. The 13th International Conference on Microelectronics.最新文献

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A CMOS single-CCII+ based VCO 基于CMOS单ccii +的压控振荡器
ICM 2001 Proceedings. The 13th International Conference on Microelectronics. Pub Date : 1900-01-01 DOI: 10.1109/ICM.2001.997513
S. Kayed, H. Ragaie, M. Abou El-Ela, F. Soliman
{"title":"A CMOS single-CCII+ based VCO","authors":"S. Kayed, H. Ragaie, M. Abou El-Ela, F. Soliman","doi":"10.1109/ICM.2001.997513","DOIUrl":"https://doi.org/10.1109/ICM.2001.997513","url":null,"abstract":"In this paper we have designed and implemented a voltage controlled oscillator (VCO) based on the single positive CMOS second generation enhanced current conveyor (CCII+) using a standard low-cost CMOS technology. The proposed circuit is fully characterized by both simulation and measurements.","PeriodicalId":360389,"journal":{"name":"ICM 2001 Proceedings. The 13th International Conference on Microelectronics.","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115863880","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
An original buffer circuit for medium and high-power applications 一个原始的缓冲电路中，大功率应用
ICM 2001 Proceedings. The 13th International Conference on Microelectronics. Pub Date : 1900-01-01 DOI: 10.1109/ICM.2001.997515
A. Rekiouak, M. Boukadoum, M. Bouchard
{"title":"An original buffer circuit for medium and high-power applications","authors":"A. Rekiouak, M. Boukadoum, M. Bouchard","doi":"10.1109/ICM.2001.997515","DOIUrl":"https://doi.org/10.1109/ICM.2001.997515","url":null,"abstract":"We present the dc characteristics of a an output stage and buffer circuit for medium to high-power applications that provides near optimal performance over a wide range of power levels and frequencies, while avoiding the use of output feedback resistors and/or thermistors for thermal compensation. The circuit uses a complementary emitter follower that operates in class-AB mode, with identical matched devices used in the bias and output stages. It provides an excellent impedance conversion between the input and output stages. For instance the load decoupling is greater than 45 dB for a circuit that uses the Tip29,30 standard complementary transistor pair. Also, the power transmission efficiency between the source and the load is maximized without the usual losses and/or distortions.","PeriodicalId":360389,"journal":{"name":"ICM 2001 Proceedings. The 13th International Conference on Microelectronics.","volume":"606 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116392135","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
An algebraic approach for test generation in iterative logic networks 迭代逻辑网络中测试生成的代数方法
ICM 2001 Proceedings. The 13th International Conference on Microelectronics. Pub Date : 1900-01-01 DOI: 10.1109/ICM.2001.997649
M.A. Seghrouchni, M. Eleuldj
{"title":"An algebraic approach for test generation in iterative logic networks","authors":"M.A. Seghrouchni, M. Eleuldj","doi":"10.1109/ICM.2001.997649","DOIUrl":"https://doi.org/10.1109/ICM.2001.997649","url":null,"abstract":"This paper deals with a generalisation of test concepts for iterative logic networks. We present an algebraic approach for test generation in iterative logic networks. The generated test is under the stuck-at fault model [Feng 81b] and the functional fault model [Eleu 88]. Three types of tests are defined : the U-test, NU-test and M-test.","PeriodicalId":360389,"journal":{"name":"ICM 2001 Proceedings. The 13th International Conference on Microelectronics.","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121505094","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Third order Butterworth filter for current-mode operation employing equal valued capacitors, equal valued resistors and unity gain active elements 采用等值电容、等值电阻和单位增益有源元件的三阶巴特沃斯滤波器
ICM 2001 Proceedings. The 13th International Conference on Microelectronics. Pub Date : 1900-01-01 DOI: 10.1109/ICM.2001.997509
H. Kuntman, O. Cicekoglu, S. Ozcan
{"title":"Third order Butterworth filter for current-mode operation employing equal valued capacitors, equal valued resistors and unity gain active elements","authors":"H. Kuntman, O. Cicekoglu, S. Ozcan","doi":"10.1109/ICM.2001.997509","DOIUrl":"https://doi.org/10.1109/ICM.2001.997509","url":null,"abstract":"This paper describes a current-mode third-order Butterworth filter realised with unity gain active elements and minimum number of passive components. All capacitors and resistors are equal valued. The core of the circuit realises HP, BP and LP functions easily. The filter exhibits high output impedance. Experimental results are included to verify theory.","PeriodicalId":360389,"journal":{"name":"ICM 2001 Proceedings. The 13th International Conference on Microelectronics.","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116992057","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Modeling techniques for substrate coupling for system-on-a-chip 片上系统衬底耦合的建模技术
ICM 2001 Proceedings. The 13th International Conference on Microelectronics. Pub Date : 1900-01-01 DOI: 10.1109/ICM.2001.997480
N. Masoumi, M. Elmasry, S. Safavi-Naeini
{"title":"Modeling techniques for substrate coupling for system-on-a-chip","authors":"N. Masoumi, M. Elmasry, S. Safavi-Naeini","doi":"10.1109/ICM.2001.997480","DOIUrl":"https://doi.org/10.1109/ICM.2001.997480","url":null,"abstract":"The demand for integrating systems on a chip functioning at high frequencies, while utilizing the recent advances of submicron IC technologies, has cost IC designers the severe problem of on-chip-crosstalk, particularly substrate coupling. This paper presents three methods for efficient modeling of substrate coupling. We develop a boundary-element method based on Green's theorem for modeling using a rapid Green's function. In addition, closed-form formulas for fast extraction of substrate parasitics in low-dense chips (disperse devices) are derived. We apply the modeling method to analysis of substrate coupling in a large RF-IC.","PeriodicalId":360389,"journal":{"name":"ICM 2001 Proceedings. The 13th International Conference on Microelectronics.","volume":"136 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131607785","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Low temperature polysilicon growth on glass suitable for TFT fabrication 适合TFT制造的低温多晶硅在玻璃上生长
ICM 2001 Proceedings. The 13th International Conference on Microelectronics. Pub Date : 1900-01-01 DOI: 10.1109/ICM.2001.997492
L. Rezaee, S. Mohajerzadeh, M. Mozafari, E. Asl Soleimani, M. Hassanzadeh
{"title":"Low temperature polysilicon growth on glass suitable for TFT fabrication","authors":"L. Rezaee, S. Mohajerzadeh, M. Mozafari, E. Asl Soleimani, M. Hassanzadeh","doi":"10.1109/ICM.2001.997492","DOIUrl":"https://doi.org/10.1109/ICM.2001.997492","url":null,"abstract":"Polysilicon films are grown on ordinary glass substrates at temperatures as low as 380/spl deg/C using a novel ultraviolet assisted metal-induced-crystallization technique. The silicon films grown using this method are suitable for the fabrication of thin film transistors. Samples prepared, consist of 1500 /spl Aring/ of silicon film deposited on 1000 /spl Aring/ silicon nitride and 2000 /spl Aring/ of chromium layers, and Ni is used as the seed for crystallization. Annealing occurred in the presence of an ultra-violet exposure and led to a high crystallinity silicon film as examined using XRD and SEM. The lateral growth as the main feature of this technique is presented using optical microscopy analysis. The preliminary results of transistor fabrication on ordinary glass is reported. Transistors fabricated using this technique show a hole mobility of 50 cm/sup 2//Vs.","PeriodicalId":360389,"journal":{"name":"ICM 2001 Proceedings. The 13th International Conference on Microelectronics.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130106191","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Dynamic signal model in the surface channel charge coupled devices 表面通道电荷耦合器件的动态信号模型
ICM 2001 Proceedings. The 13th International Conference on Microelectronics. Pub Date : 1900-01-01 DOI: 10.1109/ICM.2001.997508
S. Bri, L. Zenkouar, M. Yebari
{"title":"Dynamic signal model in the surface channel charge coupled devices","authors":"S. Bri, L. Zenkouar, M. Yebari","doi":"10.1109/ICM.2001.997508","DOIUrl":"https://doi.org/10.1109/ICM.2001.997508","url":null,"abstract":"The CCDs are used widely in special applications for very large scale integration (VLSI). In this paper, we have studied transfer charges coupled devices (CCDs) between adjacent MOS capacities under the control of an externally applied voltage. In order to show the role of the potential space inter-electrodes, a numerical program was developed and adapted to different CCD technologies.","PeriodicalId":360389,"journal":{"name":"ICM 2001 Proceedings. The 13th International Conference on Microelectronics.","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127812895","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
CAD flow for system on chip 片上系统的CAD流程
ICM 2001 Proceedings. The 13th International Conference on Microelectronics. Pub Date : 1900-01-01 DOI: 10.1109/ICM.2001.997655
P. Foulon
{"title":"CAD flow for system on chip","authors":"P. Foulon","doi":"10.1109/ICM.2001.997655","DOIUrl":"https://doi.org/10.1109/ICM.2001.997655","url":null,"abstract":"The introduction of very high deep sub-micron technology introduces a lot of new problems due to the increase in complexity. In order to handle huge chips containing 40-50 millions of transistors gathered in 30-40 blocks (commonly named IPs), multi clock domains, multi powered analog blocks, routed on 6 metal layers with some wire length measuring up to 3 cm, a hierarchical approach must be set up focusing on verification and timing closure. The author considers the following aspects of the problem: timing, data structures, top-down methodology, design teams, RTL quality, logic design standardization, DFT rules, formal proof, system verification, timing block level sign-off, and physical sign-off.","PeriodicalId":360389,"journal":{"name":"ICM 2001 Proceedings. The 13th International Conference on Microelectronics.","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126872691","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Graphics acceleration of composite transformations using reconfigurable computing 使用可重构计算的复合变换图形加速
ICM 2001 Proceedings. The 13th International Conference on Microelectronics. Pub Date : 1900-01-01 DOI: 10.1109/ICM.2001.997651
I. Damaj, H. Diab
{"title":"Graphics acceleration of composite transformations using reconfigurable computing","authors":"I. Damaj, H. Diab","doi":"10.1109/ICM.2001.997651","DOIUrl":"https://doi.org/10.1109/ICM.2001.997651","url":null,"abstract":"This paper introduces reconfigurable computing (RC) and specifically chooses one of the prototypes in this field, MorphoSys (M1) from UCI. Mapping of different linear algebraic functions, namely vector-scalar operations, onto this hardware is proposed. A performance analysis study of the M1 RC is also presented to evaluate the efficiency of the algorithm execution on the M1 system. For instance, two algorithms on an 8/spl times/8 RC array M1 were run, and numerical examples were simulated to validate our results, using the MorphoSys mULATE program, which simulates MorphoSys operations.","PeriodicalId":360389,"journal":{"name":"ICM 2001 Proceedings. The 13th International Conference on Microelectronics.","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126813973","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Lateral plasma display panels suitable for fabrication on flexible substrates 适用于柔性基板的横向等离子显示面板
ICM 2001 Proceedings. The 13th International Conference on Microelectronics. Pub Date : 1900-01-01 DOI: 10.1109/ICM.2001.997493
A. Goodarzi, A. Akhavan, S. Mohajerzadeh, E. Soleimani
{"title":"Lateral plasma display panels suitable for fabrication on flexible substrates","authors":"A. Goodarzi, A. Akhavan, S. Mohajerzadeh, E. Soleimani","doi":"10.1109/ICM.2001.997493","DOIUrl":"https://doi.org/10.1109/ICM.2001.997493","url":null,"abstract":"A pixel structure is proposed, for the first time, which is suitable for the fabrication of plasma display panels on flexible substrates such as stainless foils and PET. In this approach, the plasma is generated laterally between two electrodes. The positive and negative electrodes are realized on a single substrate and their spacing is adjusted by photolithography, so that exploiting a rigid substrate is no longer a necessity. The distance between the electrodes is not varied during substrate warping and hence fabrication of a flexible PDP is feasible. The conversion of ultra-violet light into visible color is feasible by using phosphorescent coatings. Also the structure used in this approach does not need transparent conductors like ITO. The isolation of the electrodes is possible by a silicon-oxide layer deposited using a liquid phase deposition (LPD). Also, the metallic electrodes can be realized using electroless plating suitable for large area fabrication.","PeriodicalId":360389,"journal":{"name":"ICM 2001 Proceedings. The 13th International Conference on Microelectronics.","volume":"78 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128418279","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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