S. Haji, K. Zandi, S. Mohajerzadeh, K. Naeli, E. Soleimani
{"title":"Micro-machining of [100] Si using a novel ultra-violet induced anisotropic etching in HNA solution","authors":"S. Haji, K. Zandi, S. Mohajerzadeh, K. Naeli, E. Soleimani","doi":"10.1109/ICM.2001.997495","DOIUrl":"https://doi.org/10.1109/ICM.2001.997495","url":null,"abstract":"Anisotropic etching of <100> silicon is achieved, for the first time, in the presence of ultra-violet exposure in a solution containing hydrofluoric/ nitric/ acetic acids (HNA). The HNA solution is regularly used for polishing silicon and etching polysilicon due to its isotropic etching property. In the technique proposed in this paper, called UV-HNA, the etching of silicon is enhanced in the direction determined by UV exposure. A mixture of HF/HNO/sub 3//HCOOH with a relative composition of 1:15:5 seems suitable for revealing [111] planes with an etch rate of 10 /spl mu/m/hr at 35/spl deg/C. Some anomalous behavior of etching in the presence of UV exposure is discussed. Bottom of the etched craters is hillock-free and etch rates as high as 60 /spl mu/m/hr can be achieved using higher concentration of HF acid in HNA solution. In the latter case the etching is less anisotropic and mask undercut is observed.","PeriodicalId":360389,"journal":{"name":"ICM 2001 Proceedings. The 13th International Conference on Microelectronics.","volume":"72 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126259585","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Numerical simulation of functional vertical merged MOS elements with optical supply","authors":"A. Bubennikov, V. Rakitin, A. Zykov","doi":"10.1109/ICM.2001.997646","DOIUrl":"https://doi.org/10.1109/ICM.2001.997646","url":null,"abstract":"Functional optoelectronic vertical merged MOS (OVMMOS) elements are considered with optical power supply increasing the packaging density for advanced high-speed low-power deep-submicron ULSI . Two types of new OVVMOS logical elements are proposed, analyzed and simulated. Low-voltage low-power OVMMOS with combined channels for electrons and holes to increase integration level are simulated using 2D numerical device-circuit simulators (DCS). The problems of low light power operation and optimization of OVMMOS elements are investigated using 2D-DCS.","PeriodicalId":360389,"journal":{"name":"ICM 2001 Proceedings. The 13th International Conference on Microelectronics.","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123178837","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Design and characterization of a monolithic amplifier for millimeter wave","authors":"T. Marzolf, W. Drissi, L. Zenkouar","doi":"10.1109/ICM.2001.997516","DOIUrl":"https://doi.org/10.1109/ICM.2001.997516","url":null,"abstract":"This paper focuses on design and characterization of integrated circuits working in the millimeter wave. The circuit consists of a monolithic amplifier, aimed for wireless indoor communications at 60 GHz. A calibration kit has also been developed in order to perform proper measurement on wafer.","PeriodicalId":360389,"journal":{"name":"ICM 2001 Proceedings. The 13th International Conference on Microelectronics.","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115421622","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Conception of single-lithography and space technologies of ULSI and WSI on functional nanoelectronic and optoelectronic elements","authors":"A. Bubennikov","doi":"10.1109/ICM.2001.997496","DOIUrl":"https://doi.org/10.1109/ICM.2001.997496","url":null,"abstract":"Dynamics and reforms by which the semiconductor industry could be transformed into next-generation manufacturing of Si deep-submicron and nanoelectronic ULSI and WSI are discussed For competitive Si ULSI and WSI the functional integration becomes a core design principle and cardinal simplification of manufacturing processes/equipment becomes a core technology principle. Concept of global single lithography (no-lithography on spacefab) technology for nanoelectronic complementary bipolar field-effect (CBFE), Vertical Merged MOS (VMMOS) and optoelectronic VMMOS (OVMMOS) increasing the packaging density for high-speed low-voltage ULSI and WSI is considered Technology and economics (Technonomics) concepts of space hyperhigh- vacuum technologies and processing in framework of flexible scalable no-lithography spacefab under condition of orbital flight are presented.","PeriodicalId":360389,"journal":{"name":"ICM 2001 Proceedings. The 13th International Conference on Microelectronics.","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114397096","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A new area-power efficient split-output TSPC CMOS latch for high-speed VLSI applications","authors":"B. Pontikakis, M. Nekili","doi":"10.1109/ICM.2001.997648","DOIUrl":"https://doi.org/10.1109/ICM.2001.997648","url":null,"abstract":"In this paper, a new True Single-Phase clocked (TSPC) split-output latch is introduced, and compared with existing split-output latches. The comparison is based on the criteria of robustness, area and power efficiency at high speeds. SPICE simulation is used with a 0.5-/spl mu/m CMOS process, to compare four different P-MOS split-output latches at 625 MHz, using a 3.3 V power supply. It is shown that the new split-output latch is more area-power efficient, and significantly more robust, than the existing split-output CMOS latches.","PeriodicalId":360389,"journal":{"name":"ICM 2001 Proceedings. The 13th International Conference on Microelectronics.","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121697854","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
W. Mozafari, A. Khodadadi, S. Mohajerzadeh, M. Valinasab
{"title":"Miniaturized SnO/sub 2/-based suitable for temperature-tailored lambda-ratio sensors","authors":"W. Mozafari, A. Khodadadi, S. Mohajerzadeh, M. Valinasab","doi":"10.1109/ICM.2001.997494","DOIUrl":"https://doi.org/10.1109/ICM.2001.997494","url":null,"abstract":"A sol-gel method for the fabrication of miniaturized SnO/sub 2/ sensors, compatible with Si technology, is described. The fabrication procedure consists of deposition and patterning of Pt heating elements and sensor contact pads. The SnO/sub 2/ sensing element is formed through a new sol-gel method exploiting a lift-off step for patterning. Sintering of the sensor at a temperature of 600/spl deg/C finalizes the fabrication. Preliminary results of sensor characteristics are reported. In addition, the behaviour of SnO/sub 2/ sensors fabricated using a pressed-pallet method with anomalous characteristics is addressed. The temperature-dependent response of SnO/sub 2/-based sensors as a /spl lambda/-ratio sensing device is reported. A low-high transition in the sensor conductivity, occurring at a ratio of combustible to oxygen gases away from the stoichiometric value, is reported for the first time. The ratio at which this transition arises, happens at values higher than the stoichiometric point for CO and by raising the temperature, it moves towards the stoichiometric point. This phenomenon is reversed for C/sub 2/H/sub 6/.","PeriodicalId":360389,"journal":{"name":"ICM 2001 Proceedings. The 13th International Conference on Microelectronics.","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126437371","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"High-speed low-power adder with a new logic style: pseudo dynamic logic (SDL)","authors":"G. Chaji, S. M. Fakhraie, K. smith","doi":"10.1109/ICM.2001.997506","DOIUrl":"https://doi.org/10.1109/ICM.2001.997506","url":null,"abstract":"In this paper, a high speed and low power adder is designed using a new logic-design style called Pseudo Dynamic Logic (SDL). Traditional dynamic logic is pre-charged to a default value and in the evaluation phase is changed to its real logic, However, in this new logic style, the internal nodes are charged to an intermediate pre-charge value, so that the evaluation is performed faster. A 32-bit CLA adder has been designed and simulated using HSPICE Level 49 parameters of a 0.6 /spl mu/m CMOS process. Simulated measurements on this adder show that the worst-case delay is 1.56 ns. This shows 2.1 times speed improvement and 21.2% area saving in comparison to a domino dynamic logic design implemented with the same technology.","PeriodicalId":360389,"journal":{"name":"ICM 2001 Proceedings. The 13th International Conference on Microelectronics.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126992997","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Regeneration techniques for RLC VLSI interconnects","authors":"Falah R. Awwad, M. Nekili","doi":"10.1109/ICM.2001.997647","DOIUrl":"https://doi.org/10.1109/ICM.2001.997647","url":null,"abstract":"On-chip inductance has become of significance in the design of high-speed interconnects. In this paper, three techniques are applied to regenerate an RLC interconnect in series, parallel and without regeneration. Simulations using a 0.25 /spl mu/m TSMC technology show that the parallel regeneration starts achieving a better speed than the non-regenerated line at wire lengths smaller than that achieved when the wire is serially regenerated. It also features 47% time delay saving and 96% area-delay product saving over the serial regeneration.","PeriodicalId":360389,"journal":{"name":"ICM 2001 Proceedings. The 13th International Conference on Microelectronics.","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132079741","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"FPGAs and fault tolerance","authors":"A. Doumar, H. Ito","doi":"10.1109/ICM.2001.997650","DOIUrl":"https://doi.org/10.1109/ICM.2001.997650","url":null,"abstract":"In this paper we propose a modification of the standard structure of FPGA configuration memory cells in the torus structure. The proposed modification gives the FPGA the ability to shift the configuration data inside the chip as a torus structure. We show that FPGAs having this ability give better results in terms of test, diagnosis and defect/fault tolerance. Only faults occurring in configurable logic blocks are considered in this paper. Testing and diagnosing faults in the chips having the proposed modification are achieved by loading typically only one set of configuration data. The other configuration data required for test and diagnosis are obtained by shifting the first set inside the chip. This makes test and diagnosis faster. Our simulation results show that this way of testing is especially effective when the complexity of the configurable logic blocks or the size increases. On the other hand, the defect tolerance is transparent to the user and is achieved with a very high yield, while the fault tolerance is achieved on chip with the original user configuration data and without hardware intervention. Additionally, using 0.5 /spl mu/m technology, we have designed and manufactured a prototype of an FPGA similar to the Xilinx 4000 series structure having the ability to shift data.","PeriodicalId":360389,"journal":{"name":"ICM 2001 Proceedings. The 13th International Conference on Microelectronics.","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133752915","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
H. Saleh, E. Zimmermann, G. Brandenburg, H. Halling
{"title":"Efficient FPGA-based multistage two-path decimation filter for noise thermometer","authors":"H. Saleh, E. Zimmermann, G. Brandenburg, H. Halling","doi":"10.1109/ICM.2001.997512","DOIUrl":"https://doi.org/10.1109/ICM.2001.997512","url":null,"abstract":"This paper introduces an efficient Field Programmable Gate Array (FPGA) realization of a multistage decimation filter with narrow passband and very narrow transition band for noise thermometer application. The filter is composed of six stages, the first five stages are two-coefficient half-band filters and the last stage is a sharper transition half-band filter. For the last stage, we proposed a binary-scaled four-coefficient filter and two cascaded two-coefficient filters. The frequency responses and implementation area of different half-band filters are compared. In contrast to multirate techniques, we realized a frequency masking single rate filter, which consumes a larger area. The measured frequency response of the implemented filter is compared with the calculated one.","PeriodicalId":360389,"journal":{"name":"ICM 2001 Proceedings. The 13th International Conference on Microelectronics.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131315816","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}