{"title":"一种用于高速VLSI应用的新型面积功率高效分路输出TSPC CMOS锁存器","authors":"B. Pontikakis, M. Nekili","doi":"10.1109/ICM.2001.997648","DOIUrl":null,"url":null,"abstract":"In this paper, a new True Single-Phase clocked (TSPC) split-output latch is introduced, and compared with existing split-output latches. The comparison is based on the criteria of robustness, area and power efficiency at high speeds. SPICE simulation is used with a 0.5-/spl mu/m CMOS process, to compare four different P-MOS split-output latches at 625 MHz, using a 3.3 V power supply. It is shown that the new split-output latch is more area-power efficient, and significantly more robust, than the existing split-output CMOS latches.","PeriodicalId":360389,"journal":{"name":"ICM 2001 Proceedings. The 13th International Conference on Microelectronics.","volume":"11 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":"{\"title\":\"A new area-power efficient split-output TSPC CMOS latch for high-speed VLSI applications\",\"authors\":\"B. Pontikakis, M. Nekili\",\"doi\":\"10.1109/ICM.2001.997648\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper, a new True Single-Phase clocked (TSPC) split-output latch is introduced, and compared with existing split-output latches. The comparison is based on the criteria of robustness, area and power efficiency at high speeds. SPICE simulation is used with a 0.5-/spl mu/m CMOS process, to compare four different P-MOS split-output latches at 625 MHz, using a 3.3 V power supply. It is shown that the new split-output latch is more area-power efficient, and significantly more robust, than the existing split-output CMOS latches.\",\"PeriodicalId\":360389,\"journal\":{\"name\":\"ICM 2001 Proceedings. The 13th International Conference on Microelectronics.\",\"volume\":\"11 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1900-01-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"4\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"ICM 2001 Proceedings. The 13th International Conference on Microelectronics.\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICM.2001.997648\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"ICM 2001 Proceedings. The 13th International Conference on Microelectronics.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICM.2001.997648","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 4
摘要
本文介绍了一种新的真单相时钟(TSPC)分路输出锁存器，并与现有的分路输出锁存器进行了比较。这种比较是基于高速时的鲁棒性、面积和功率效率的标准。SPICE仿真与0.5-/spl μ m CMOS工艺一起使用，使用3.3 V电源在625 MHz下比较四种不同的P-MOS分路输出锁存器。结果表明，与现有的分路输出CMOS锁存器相比，新的分路输出锁存器具有更高的面积功率效率，并且显着提高了鲁棒性。
A new area-power efficient split-output TSPC CMOS latch for high-speed VLSI applications
In this paper, a new True Single-Phase clocked (TSPC) split-output latch is introduced, and compared with existing split-output latches. The comparison is based on the criteria of robustness, area and power efficiency at high speeds. SPICE simulation is used with a 0.5-/spl mu/m CMOS process, to compare four different P-MOS split-output latches at 625 MHz, using a 3.3 V power supply. It is shown that the new split-output latch is more area-power efficient, and significantly more robust, than the existing split-output CMOS latches.
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