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ICM 2001 Proceedings. The 13th International Conference on Microelectronics.最新文献

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CMP provides the access to advanced low cost manufacturing CMP为先进的低成本制造提供了途径
ICM 2001 Proceedings. The 13th International Conference on Microelectronics. Pub Date : 2001-10-29 DOI: 10.1109/ICM.2001.997477
K. Torki
{"title":"CMP provides the access to advanced low cost manufacturing","authors":"K. Torki","doi":"10.1109/ICM.2001.997477","DOIUrl":"https://doi.org/10.1109/ICM.2001.997477","url":null,"abstract":"CMP aims at providing universities, research laboratories and industries with the possibility of having their integrated circuit projects fabricated for prototyping and low volume production. Presently, users are serviced for CMOS double layer poly/double layer metal (DLP/DLM) 0.8 /spl mu/m, DLM/TLM 0.6 /spl mu/m, DLP/4LM 0.35 /spl mu/m, SLP/6LM 0.25 /spl mu/m, SLP/6LM 0.18 /spl mu/m, BiCMOS DLP/DLM 0.8 /spl mu/m, SiGe HBT 0.8 /spl mu/m DLP/DLM, SiGe HBT 0.35 /spl mu/m SLP/5LM and GaAs HEMT 0.2 /spl mu/m. About 40 multi-project runs are offered per year. Micro Electro Mechanical Systems (MEMS) are also provided in standard CMP runs in CMOS DLP/DLM 0.8 /spl mu/m and 0.6 /spl mu/m, BiCMOS DLP/DLM 0.8 /spl mu/m and HEMT GaAs 0.2 /spl mu/m, using compatible front-side bulk micro-machining. MUMPS is offered as a surface micro-machining process, allowing one to integrate MEMS only microstructures. Finally, the main processes for Multi-Chip Modules (MCMs) are also available through CMP.","PeriodicalId":360389,"journal":{"name":"ICM 2001 Proceedings. The 13th International Conference on Microelectronics.","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128973906","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Performance indicators for designing CMOS logic 设计CMOS逻辑的性能指标
ICM 2001 Proceedings. The 13th International Conference on Microelectronics. Pub Date : 2001-10-29 DOI: 10.1109/ICM.2001.997497
P. Maurine, N. Azémard, D. Auvergne
{"title":"Performance indicators for designing CMOS logic","authors":"P. Maurine, N. Azémard, D. Auvergne","doi":"10.1109/ICM.2001.997497","DOIUrl":"https://doi.org/10.1109/ICM.2001.997497","url":null,"abstract":"The fast evolution of CMOS processes makes mandatory the use of metrics for performance as easy and robust indicators to evaluate the different alternatives at all the steps of the design flow. In this paper we present performance indicators used as well to evaluate the performances of CMOS design and to predict their evolution during process migration. These indicators are defined for process speed characterization, cell efficiency in terms of load and duration time of input controlling signals and for supply voltage sensitivity. Examples of validation are given for different processes ranging from 1.2 to 0.18 /spl mu/m.","PeriodicalId":360389,"journal":{"name":"ICM 2001 Proceedings. The 13th International Conference on Microelectronics.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-10-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131314548","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
The degradation of MOSFETs induced by the via etching of interlayer low-k polymers 层间低钾聚合物的蚀刻诱导mosfet的降解
ICM 2001 Proceedings. The 13th International Conference on Microelectronics. Pub Date : 1900-01-01 DOI: 10.1109/ICM.2001.997498
L. Trabzon, O. Awadelkarim
{"title":"The degradation of MOSFETs induced by the via etching of interlayer low-k polymers","authors":"L. Trabzon, O. Awadelkarim","doi":"10.1109/ICM.2001.997498","DOIUrl":"https://doi.org/10.1109/ICM.2001.997498","url":null,"abstract":"We report on the effects of via etching through two low-k polymers (FLARE and BCB) used as interlayer dielectrics, on the performance of 0.35 /spl mu/m long n-channel MOSFETs with 45 /spl Aring/ thick gate oxides. It is observed that the via etching of the polymers damages the MOSFET and that this damage is severer in the case of BCB via etching. The inclusion of an insulating Si/sub 3/N/sub 4/ layer underneath the polymer is found to be very effective in reducing the MOSFET's damage. Alternatively, annealing in forming gas at 350/spl deg/C for 30 min after the via etching can further eliminate device damage.","PeriodicalId":360389,"journal":{"name":"ICM 2001 Proceedings. The 13th International Conference on Microelectronics.","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115278451","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
High frequency and high Q CMOS GM-C bandpass filter with automatic on-chip tuning 高频高Q CMOS GM-C带通滤波器，具有片上自动调谐功能
ICM 2001 Proceedings. The 13th International Conference on Microelectronics. Pub Date : 1900-01-01 DOI: 10.1109/ICM.2001.997514
H. Elhallabi, M. Sawan
{"title":"High frequency and high Q CMOS GM-C bandpass filter with automatic on-chip tuning","authors":"H. Elhallabi, M. Sawan","doi":"10.1109/ICM.2001.997514","DOIUrl":"https://doi.org/10.1109/ICM.2001.997514","url":null,"abstract":"A maximally flat magnitude 70 MHz fourth-order bandpass filter with an on-chip automatic tuning system is presented. The input equivalent noise is 19 /spl mu/V/sqr(Hz) which shows that the nonlinearity at the input of the filter is very small. The IIP3 (the input level of the third-order intercept point) of the filter is -9.25dBm. The complete system operates with a supply voltage of 2.2 V. All this has been achieved due to the use of a low distortion transconductor, and the realization of an advanced on-chip automatic tuning system for both frequency and bandwidth control. The whole circuit has been implemented in 0.35 /spl mu/m CMOS technology available through the Canadian Microelectronics Corporation (CMC).","PeriodicalId":360389,"journal":{"name":"ICM 2001 Proceedings. The 13th International Conference on Microelectronics.","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115217976","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
New hardware/software design methodologies 新的硬件/软件设计方法
ICM 2001 Proceedings. The 13th International Conference on Microelectronics. Pub Date : 1900-01-01 DOI: 10.1109/ICM.2001.997473
E. Aboulhamid
{"title":"New hardware/software design methodologies","authors":"E. Aboulhamid","doi":"10.1109/ICM.2001.997473","DOIUrl":"https://doi.org/10.1109/ICM.2001.997473","url":null,"abstract":"This paper describes the use of the multi-paradigms aspects of SystemC to develop hardware libraries, to reuse designs, to accelerate simulation, and to allow efficient design space exploration both at the RTL and architectural levels. Concepts of commonality and variation are used to compare SystemC capabilities to those of VHDL.","PeriodicalId":360389,"journal":{"name":"ICM 2001 Proceedings. The 13th International Conference on Microelectronics.","volume":"153 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116726023","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Electroluminescence analysis of neutron irradiation of JFETs jfet中子辐照的电致发光分析
ICM 2001 Proceedings. The 13th International Conference on Microelectronics. Pub Date : 1900-01-01 DOI: 10.1109/ICM.2001.997490
A. Ahaitouf, M. Lahbabi, M. Fliyou, E. Abarkan, A. Hoffmann, J. Charles
{"title":"Electroluminescence analysis of neutron irradiation of JFETs","authors":"A. Ahaitouf, M. Lahbabi, M. Fliyou, E. Abarkan, A. Hoffmann, J. Charles","doi":"10.1109/ICM.2001.997490","DOIUrl":"https://doi.org/10.1109/ICM.2001.997490","url":null,"abstract":"Electroluminescence (EL) measurements are used as a sensitive technique for the study of fast neutron irradiation of silicon n-channel JFET overlaid by a passivation oxide layer. By theoretical simulations, it is demonstrated that neutron irradiation result in two effects: an increase of the refractive index of the passivation oxide and the introduction of deep level traps which reduce the emitted intensities by reduction of the mobility of hot carriers.","PeriodicalId":360389,"journal":{"name":"ICM 2001 Proceedings. The 13th International Conference on Microelectronics.","volume":"122 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129091260","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A sub-0.5 V dynamic threshold PMOS (DTPMOS) scheme for bulk CMOS technologies 一种用于批量CMOS技术的亚0.5 V动态阈值PMOS (DTPMOS)方案
ICM 2001 Proceedings. The 13th International Conference on Microelectronics. Pub Date : 1900-01-01 DOI: 10.1109/ICM.2001.997491
M. Elgebaly, M. Sachdev
{"title":"A sub-0.5 V dynamic threshold PMOS (DTPMOS) scheme for bulk CMOS technologies","authors":"M. Elgebaly, M. Sachdev","doi":"10.1109/ICM.2001.997491","DOIUrl":"https://doi.org/10.1109/ICM.2001.997491","url":null,"abstract":"A new dynamic threshold PMOS (DTPMOS) scheme is presented. In this scheme, the gate of a PMOS transistor is connected to its well in a conventional bulk CMOS technology. This technique results in improved switching speed compared to conventional CMOS in the sub-0.5 V regime. A 32-bit carry skip adder is designed for low voltage, low energy applications using the DTPMOS scheme. This adder consumes only 0.25 pJ of energy at a frequency of 5 MHz. The proposed design results in a 64% reduction in delay and 26% saving in energy compared to the conventional CMOS implementation.","PeriodicalId":360389,"journal":{"name":"ICM 2001 Proceedings. The 13th International Conference on Microelectronics.","volume":"67 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124472452","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
Multimedia multi-challenges 多媒体multi-challenges
ICM 2001 Proceedings. The 13th International Conference on Microelectronics. Pub Date : 1900-01-01 DOI: 10.1109/ICM.2001.997474
J. Chateau
{"title":"Multimedia multi-challenges","authors":"J. Chateau","doi":"10.1109/ICM.2001.997474","DOIUrl":"https://doi.org/10.1109/ICM.2001.997474","url":null,"abstract":"The author describes the impact of multimedia on the microelectronics industry, particularly the integration of the \"old\" segments: computer, consumer, telecommunication, and automotive. Semiconductor companies have been obliged to integrate complete systems on chips and to develop software, leaving most of the traditional silicon design problems to the EDA community at least for the digital portions. Some examples are presented, including pocket multimedia.","PeriodicalId":360389,"journal":{"name":"ICM 2001 Proceedings. The 13th International Conference on Microelectronics.","volume":"284 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132233929","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Comparison of bulk and SOI CMOS technologies in a DSP processor circuit implementation 块体和SOI CMOS技术在DSP处理器电路实现中的比较
ICM 2001 Proceedings. The 13th International Conference on Microelectronics. Pub Date : 1900-01-01 DOI: 10.1109/ICM.2001.997499
{"title":"Comparison of bulk and SOI CMOS technologies in a DSP processor circuit implementation","authors":"","doi":"10.1109/ICM.2001.997499","DOIUrl":"https://doi.org/10.1109/ICM.2001.997499","url":null,"abstract":"Silicon-on-insulator (SOI) CMOS technologies are very attractive options for implementing high-speed digital integrated circuits for low-power applications. This paper presents the layout migration of a DSP processor chip from a 0.6 /spl mu/m bulk CMOS to a 0.5 /spl mu/m SOI CMOS technology. The layout migration and verification are described and the two CMOS designs are compared using two main criteria: circuit speed and average power consumption. For nominal supply voltages, the simulations suggest that the SOI circuit can operate at a speed of 98 MHz which is 51 % higher than that of the original (65 MHz). The average power consumption is 35 % lower in the SOI circuit by using 3.3 V and 35 MHz for both SOI and bulk CMOS designs.","PeriodicalId":360389,"journal":{"name":"ICM 2001 Proceedings. The 13th International Conference on Microelectronics.","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134434173","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 19
Worst-case SPICE model generation for a process in development using Athena, Atlas, Utmost and Spayn 使用Athena, Atlas, extremes和Spayn为开发过程生成最坏情况SPICE模型
ICM 2001 Proceedings. The 13th International Conference on Microelectronics. Pub Date : 1900-01-01 DOI: 10.1109/ICM.2001.997475
F. Duvivier, E. Guichard
{"title":"Worst-case SPICE model generation for a process in development using Athena, Atlas, Utmost and Spayn","authors":"F. Duvivier, E. Guichard","doi":"10.1109/ICM.2001.997475","DOIUrl":"https://doi.org/10.1109/ICM.2001.997475","url":null,"abstract":"The main objective of this work is to use Technology CAD (TCAD) to generate statistical SPICE models for a developing deep sub-micron CMOS technology. The aim is to use the same extraction strategy and tools for TCAD data as would be used for measurement data. The ability to estimate the worst-case SPICE models for a process, based on the physical variations of process parameters, is critical for the prediction of statistical circuit performance variabilities. Silvaco's line of simulation products enables process engineers to predict the effects of process changes on device performances. Changes in process parameters and mask variation are described using the Virtual Wafer Fab (VWF) framework. The ATHENA process simulator, the ATLAS device simulator and the UTMOST parameter extractor are included in this framework. The SPICE models extracted by UTMOST as part of a VWF experiment may be imported into SPAYN for a detailed statistical analysis and model parameter sets corresponding to various process \"corner\" are derived. SPAYN, in turn, can be linked to our circuit simulator SMARTSPICE. This allow circuit performance to be analyzed using the \"corner\" models so that worst-case circuit performance for any particular circuit application can be identified. Monte Carlo or user defined circuit simulations, using correlated parameter sets arising from the analysis of the extracted parameters (Principal Component Analysis for example), are also run directly from SPAYN.","PeriodicalId":360389,"journal":{"name":"ICM 2001 Proceedings. The 13th International Conference on Microelectronics.","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126355579","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
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