Worst-case SPICE model generation for a process in development using Athena, Atlas, Utmost and Spayn

Abstract

The main objective of this work is to use Technology CAD (TCAD) to generate statistical SPICE models for a developing deep sub-micron CMOS technology. The aim is to use the same extraction strategy and tools for TCAD data as would be used for measurement data. The ability to estimate the worst-case SPICE models for a process, based on the physical variations of process parameters, is critical for the prediction of statistical circuit performance variabilities. Silvaco's line of simulation products enables process engineers to predict the effects of process changes on device performances. Changes in process parameters and mask variation are described using the Virtual Wafer Fab (VWF) framework. The ATHENA process simulator, the ATLAS device simulator and the UTMOST parameter extractor are included in this framework. The SPICE models extracted by UTMOST as part of a VWF experiment may be imported into SPAYN for a detailed statistical analysis and model parameter sets corresponding to various process "corner" are derived. SPAYN, in turn, can be linked to our circuit simulator SMARTSPICE. This allow circuit performance to be analyzed using the "corner" models so that worst-case circuit performance for any particular circuit application can be identified. Monte Carlo or user defined circuit simulations, using correlated parameter sets arising from the analysis of the extracted parameters (Principal Component Analysis for example), are also run directly from SPAYN.