Performance indicators for designing CMOS logic

The fast evolution of CMOS processes makes mandatory the use of metrics for performance as easy and robust indicators to evaluate the different alternatives at all the steps of the design flow. In this paper we present performance indicators used as well to evaluate the performances of CMOS design and to predict their evolution during process migration. These indicators are defined for process speed characterization, cell efficiency in terms of load and duration time of input controlling signals and for supply voltage sensitivity. Examples of validation are given for different processes ranging from 1.2 to 0.18 /spl mu/m.