{"title":"一种用于批量CMOS技术的亚0.5 V动态阈值PMOS (DTPMOS)方案","authors":"M. Elgebaly, M. Sachdev","doi":"10.1109/ICM.2001.997491","DOIUrl":null,"url":null,"abstract":"A new dynamic threshold PMOS (DTPMOS) scheme is presented. In this scheme, the gate of a PMOS transistor is connected to its well in a conventional bulk CMOS technology. This technique results in improved switching speed compared to conventional CMOS in the sub-0.5 V regime. A 32-bit carry skip adder is designed for low voltage, low energy applications using the DTPMOS scheme. This adder consumes only 0.25 pJ of energy at a frequency of 5 MHz. The proposed design results in a 64% reduction in delay and 26% saving in energy compared to the conventional CMOS implementation.","PeriodicalId":360389,"journal":{"name":"ICM 2001 Proceedings. The 13th International Conference on Microelectronics.","volume":"67 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"12","resultStr":"{\"title\":\"A sub-0.5 V dynamic threshold PMOS (DTPMOS) scheme for bulk CMOS technologies\",\"authors\":\"M. Elgebaly, M. Sachdev\",\"doi\":\"10.1109/ICM.2001.997491\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A new dynamic threshold PMOS (DTPMOS) scheme is presented. In this scheme, the gate of a PMOS transistor is connected to its well in a conventional bulk CMOS technology. This technique results in improved switching speed compared to conventional CMOS in the sub-0.5 V regime. A 32-bit carry skip adder is designed for low voltage, low energy applications using the DTPMOS scheme. This adder consumes only 0.25 pJ of energy at a frequency of 5 MHz. The proposed design results in a 64% reduction in delay and 26% saving in energy compared to the conventional CMOS implementation.\",\"PeriodicalId\":360389,\"journal\":{\"name\":\"ICM 2001 Proceedings. The 13th International Conference on Microelectronics.\",\"volume\":\"67 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1900-01-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"12\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"ICM 2001 Proceedings. The 13th International Conference on Microelectronics.\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICM.2001.997491\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"ICM 2001 Proceedings. The 13th International Conference on Microelectronics.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICM.2001.997491","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A sub-0.5 V dynamic threshold PMOS (DTPMOS) scheme for bulk CMOS technologies
A new dynamic threshold PMOS (DTPMOS) scheme is presented. In this scheme, the gate of a PMOS transistor is connected to its well in a conventional bulk CMOS technology. This technique results in improved switching speed compared to conventional CMOS in the sub-0.5 V regime. A 32-bit carry skip adder is designed for low voltage, low energy applications using the DTPMOS scheme. This adder consumes only 0.25 pJ of energy at a frequency of 5 MHz. The proposed design results in a 64% reduction in delay and 26% saving in energy compared to the conventional CMOS implementation.
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