{"title":"Microelectronics to build smart medical devices","authors":"M. Sawan","doi":"10.1109/ICM.2001.997476","DOIUrl":"https://doi.org/10.1109/ICM.2001.997476","url":null,"abstract":"Summary form only given. The bladder controller and the visual cortical stimulator are the main subjects of research activities of the PolySTIM team at the Ecole Polytechnique de Montreal. Such devices are dedicated to recuperate or enhance neuromuscular functions in patients by means of peripherals or central nervous systems. While the bladder controllor is dedicated to recuperate voiding and retention functions on paralyzed patients, the electronic visual stimulator is dedicated to create adequate vision for totally blind patients. Neural peripheral sacral stimulation is applied to recover the bladder function, but direct stimulation of the brain is the basic principle of the visual cortex stimulator proposed by PolySTIM. The author elaborates the design and validation of the visual implant that involves an advanced stimulator mounted on a matrix of 25/spl times/25 microelectrodes which are implanted on the visuel cortex to recover partial vision for blind patients.","PeriodicalId":360389,"journal":{"name":"ICM 2001 Proceedings. The 13th International Conference on Microelectronics.","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128137005","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Novel varactors in BiCMOS technology with improved characteristics","authors":"J. Maget, R. Kraus","doi":"10.1109/ICM.2001.997486","DOIUrl":"https://doi.org/10.1109/ICM.2001.997486","url":null,"abstract":"The first true BiCMOS varactor combining typical elements of CMOS and bipolar Technologies is presented. Several test structures and different versions have been manufactured in a 0.25 /spl mu/m BiCMOS technology and measured. The first type of the proposed novel varactor structure features a capacitance tuning range (ratio of maximum to minimum achievable values) C/sub max//C/sub min/ of 3.8:1 with a minimum quality factor Q of 32 and a maximum Q of 273. Choosing the second type of the herein presented novel device, allows quality factors from 6 to above 500, while increasing the capacitance tuning range to an outstanding value of 10.11:1.","PeriodicalId":360389,"journal":{"name":"ICM 2001 Proceedings. The 13th International Conference on Microelectronics.","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114543870","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A high performance current differencing buffered amplifier","authors":"N. Tarim, H. Kuntman","doi":"10.1109/ICM.2001.997510","DOIUrl":"https://doi.org/10.1109/ICM.2001.997510","url":null,"abstract":"This paper presents a high performance current differencing buffered amplifier (CDBA), a recently reported active component, especially suitable for analog signal processing applications. It employs two second generation current conveyors (CCII) and a voltage buffer. The circuit contains only MOS transistors and is designed to be implemented in CMOS technology. Simulated device characteristics show that the proposed circuit exhibits a very good performance and offers new opportunities for analog circuit designers. A first-order all-pass filter circuit was chosen as an application example in order to demonstrate the performance of the CDBA. It will be seen that simulation results verify the theory.","PeriodicalId":360389,"journal":{"name":"ICM 2001 Proceedings. The 13th International Conference on Microelectronics.","volume":"181 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114748963","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Interface state degradation of metal/ultra-thin oxide/semiconductor structures under electron injections at high field","authors":"K. Kassmi, R. Maimouni","doi":"10.1109/ICM.2001.997489","DOIUrl":"https://doi.org/10.1109/ICM.2001.997489","url":null,"abstract":"In this paper we analyze the interface states of metal/ultra thin oxide/semiconductor structures and their degradation under electron injection from the metal or the semiconductor, by the Fowler-Nordheim effect, at high electric field (>10 MV/cm). The metal used is chromium and the oxide layer thickness is in the range of 60 /spl Aring/-130 /spl Aring/. Before injection the energy distribution of the interface states in the semiconductor gap presents a peak of energy of 0.25 eV above the semiconductor valence band edge. The peak density (Nssmax) decreases with the oxide thickness. After injection the degradation of the Nssmax density depends on the oxide thickness, and increases with injected charge independently of the injected field and the polarization mode (V<0, V>0) of the structure for the high injected charge (Qinj>2.10/sup -1/ c/cm/sup 2/). The injection influence on the interface state density (Nssmid) at mid gap is not important. The Nssmid density is lower than 10/sup 10/ eV/sup -1/ cm/sup -2/ for all the injection charges (V<0, V>0). Also, we showed that the sensitivity to the degradation by electron injection decreases with the oxide thickness. In comparing with the literature results, we deduced a lower interface state density for our structures, and a satisfactory sensitivity to the degradation to high injecting fields.","PeriodicalId":360389,"journal":{"name":"ICM 2001 Proceedings. The 13th International Conference on Microelectronics.","volume":"90 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124645804","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Estimation and optimization of delay in popular CMOS logic styles","authors":"M. Shams, M. Elmasry","doi":"10.1109/ICM.2001.997484","DOIUrl":"https://doi.org/10.1109/ICM.2001.997484","url":null,"abstract":"This paper presents a unified model for delay estimation in various CMOS logic styles. It also derives closed-form optimal transistor sizing formulas for minimizing the delay in each logic style. The paper demonstrates the use of these formulas for delay optimization in mixed logic-style CMOS circuits. Mixing CMOS logic styles in a circuit has the potential of improving performance and reducing energy dissipation and area.","PeriodicalId":360389,"journal":{"name":"ICM 2001 Proceedings. The 13th International Conference on Microelectronics.","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128872093","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
J. Abouchabaka, R. Aboulaich, A. Nachaoui, A. Souissi
{"title":"The study of a drift-diffusion model","authors":"J. Abouchabaka, R. Aboulaich, A. Nachaoui, A. Souissi","doi":"10.1109/ICM.2001.997485","DOIUrl":"https://doi.org/10.1109/ICM.2001.997485","url":null,"abstract":"This work proposes a theoretical and a numerical study of a decoupled algorithm in order to approximate a free boundary separating the depletion region and the charge neutrality region in a field effect transistor of MESFET type. In order to do that, a simplified drift-diffusion model is used. In this work we prove the convergence of the previous algorithm and we present some numerical results.","PeriodicalId":360389,"journal":{"name":"ICM 2001 Proceedings. The 13th International Conference on Microelectronics.","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122410990","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
M. Acero, A. Errachid, T. Baldi, J. Esteve, N. Garcia, T. Diez-Caballero
{"title":"Differential injection analysis based on backside-contacted ISFETs","authors":"M. Acero, A. Errachid, T. Baldi, J. Esteve, N. Garcia, T. Diez-Caballero","doi":"10.1109/ICM.2001.997502","DOIUrl":"https://doi.org/10.1109/ICM.2001.997502","url":null,"abstract":"In this paper a differential injection analysis (DIA) based on ISFETs is presented. The method consists of differential measurements in two parallel micro-cells with identical ISFET sensors connected in the output port. Sample is injected in the first cell as in conventional FIA systems, while in the second cell it is injected as reference buffer. In this way, a simple method for differential measurements is implemented avoiding the need of a reference electrode. By using BSC-ISFET technology integrated with tubular microcell, parallel cells with identical ISFETs are obtained in batch-fabrication.","PeriodicalId":360389,"journal":{"name":"ICM 2001 Proceedings. The 13th International Conference on Microelectronics.","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126714203","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"FPGA-based IC design for inverter with vector modulation technique","authors":"M. W. Kharrat, M. Loulou, N. Masmoudi, L. Kamoun","doi":"10.1109/ICM.2001.997518","DOIUrl":"https://doi.org/10.1109/ICM.2001.997518","url":null,"abstract":"Presents an application of a Xilinx FPGA device, in the CX4000 family, producing pulse width modulation (PWM) signals with the vector modulation technique for an IGBT inverter. Using a single FPGA chip for the practical implementation of the modulator, rather than a system consisting of microprocessor and external memory, has many advantages including less use of power and space, short design time, greater speed and reliability. The designed circuit can generate PWM signals, and also, the input values used to adjust output signal may be obtained through a microprocessor port. A comparison between the implementation on DSP and on FPGA at the level time will be made to validate the use of the FPGA.","PeriodicalId":360389,"journal":{"name":"ICM 2001 Proceedings. The 13th International Conference on Microelectronics.","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128324059","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Automating the verification of parameterized hardware using a hybrid tool","authors":"P. Curzon, S. Tahar","doi":"10.1109/ICM.2001.997659","DOIUrl":"https://doi.org/10.1109/ICM.2001.997659","url":null,"abstract":"We outline how a hybrid formal hardware verification tool that links an interactive theorem prover and an automated hardware verification tool, can verify parameterized circuits containing replicated components. We show that the approach integrates well with the hierarchical proof approach embodied in the hybrid tool.","PeriodicalId":360389,"journal":{"name":"ICM 2001 Proceedings. The 13th International Conference on Microelectronics.","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114638804","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A hardware accelerator for DSP system design: University of Tehran DSP Hardware Emulator (UTDHE)","authors":"H.R. Mahdiany, A. Hormati, S. M. Fakhraie","doi":"10.1109/ICM.2001.997507","DOIUrl":"https://doi.org/10.1109/ICM.2001.997507","url":null,"abstract":"DSP systems play an important role in modern industry and new DSP systems should be designed rapidly to overcome the new necessities that arise. However, the process of designing a DSP system is very time consuming and most of this time is wasted on simulating and debugging of such complex systems. We have designed and implemented a system that makes it possible to emulate and debug large DSP designs (up to 250,000 gates) as fast as possible. With this system, the user can test his or her DSP scheme with fast hardware emulation instead of slow software simulation and as a result reduce time to market significantly. The designed DSP HWE system can emulate complex DSPs that operate at different clock rates and need up to four modules of external memories. It is important to note that low-level simulation of such systems needs a long simulation time, making it impossible to completely simulate and test such designs. As a result of this work, such prohibitive factor has been eliminated.","PeriodicalId":360389,"journal":{"name":"ICM 2001 Proceedings. The 13th International Conference on Microelectronics.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125759298","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}