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ICM 2001 Proceedings. The 13th International Conference on Microelectronics.最新文献

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Minimizing register requirements for synchronous circuits derived using software pipelining techniques 使用软件流水线技术最小化同步电路的寄存器要求
ICM 2001 Proceedings. The 13th International Conference on Microelectronics. Pub Date : 1900-01-01 DOI: 10.1109/ICM.2001.997657
N. Chabini, E. Aboulhamid, Y. Savaria
{"title":"Minimizing register requirements for synchronous circuits derived using software pipelining techniques","authors":"N. Chabini, E. Aboulhamid, Y. Savaria","doi":"10.1109/ICM.2001.997657","DOIUrl":"https://doi.org/10.1109/ICM.2001.997657","url":null,"abstract":"A method based on software pipelining has been recently proposed to optimize mono-phase clocked sequential circuits. The resulting circuits are multi-phase clocked sequential circuits, where all clocks have the same period. To preserve functionality of the original circuit, registers must be placed according to a correct schedule. This schedule also ensures maximum throughput. In that method, it is a question of (1) how to determine a schedule that requires the minimum number of registers, and (2) how to place these registers optimally. In this paper, problems (1) and (2) are tackled simultaneously. More precisely, we deal with the problem of determining schedules with the minimum register requirements, where the optimal register placement is done during the schedule determination. To optimally solve that problem, we provide a mixed integer linear program that we use to derive a linear program, which is polynomial-time solvable. Experimental results confirm the effectiveness of the approach, and show that significant reductions of the number of registers can be obtained.","PeriodicalId":360389,"journal":{"name":"ICM 2001 Proceedings. The 13th International Conference on Microelectronics.","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126530475","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Theoretical modeling of PtSi/porous Schottky detectors PtSi/多孔肖特基探测器的理论建模
ICM 2001 Proceedings. The 13th International Conference on Microelectronics. Pub Date : 1900-01-01 DOI: 10.1109/ICM.2001.997483
F. Raissi, M. Mohtashami Far
{"title":"Theoretical modeling of PtSi/porous Schottky detectors","authors":"F. Raissi, M. Mohtashami Far","doi":"10.1109/ICM.2001.997483","DOIUrl":"https://doi.org/10.1109/ICM.2001.997483","url":null,"abstract":"The current-voltage characteristic of PtSi/porous Si Schottky detectors has been modeled. It is assumed that high electric fields are developed at sharp and irregular edges of the porous surface, causing avalanche and tunneling breakdown. The shape of the I-V curve, its change with temperature, its response to near and far IR, and the large quantum efficiency are satisfactorily explained by this model.","PeriodicalId":360389,"journal":{"name":"ICM 2001 Proceedings. The 13th International Conference on Microelectronics.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124388485","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Power supply wires self-heating analysis 电源线自热分析
ICM 2001 Proceedings. The 13th International Conference on Microelectronics. Pub Date : 1900-01-01 DOI: 10.1109/ICM.2001.997501
M. Casu, M. Graziano, M. Roch, F. Viglione
{"title":"Power supply wires self-heating analysis","authors":"M. Casu, M. Graziano, M. Roch, F. Viglione","doi":"10.1109/ICM.2001.997501","DOIUrl":"https://doi.org/10.1109/ICM.2001.997501","url":null,"abstract":"Self-heating is one of the major problems of high performance ICs due to scaled feature sizes, interconnect congestion and increased current densities. As a consequence, particular attention is necessary to avoid reliability drawbacks. In this paper we report analysis results achieved evaluating self-heating of power supply busses in presence of current injection related to different working conditions. This set of estimations has been realized considering three distinct metal layers and two logic families. This analysis and optimization methodology and results will be inserted in a developing tool for power supply noise evaluation and reduction, with the aim to take into account thermal phenomena while optimizing power bus sizing and routing for noise avoidance.","PeriodicalId":360389,"journal":{"name":"ICM 2001 Proceedings. The 13th International Conference on Microelectronics.","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123630219","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Testing FPGA based reconfigurable system within run time applications 在运行时应用中测试基于FPGA的可重构系统
ICM 2001 Proceedings. The 13th International Conference on Microelectronics. Pub Date : 1900-01-01 DOI: 10.1109/ICM.2001.997653
A. Doumar, H. Ito
{"title":"Testing FPGA based reconfigurable system within run time applications","authors":"A. Doumar, H. Ito","doi":"10.1109/ICM.2001.997653","DOIUrl":"https://doi.org/10.1109/ICM.2001.997653","url":null,"abstract":"We introduce a technique for testing partially reconfigurable FPGAs. The test technique is intended to be applied in reconfigurable systems in run time applications. Normally, in reconfigurable systems, each FPGA executes many tasks sequentially. Therefore, it is configured many times in run time applications. We propose that each FPGA is tested just before each configuration. The whole system remains functional because other FPGAs are still in function when the target FPGA is under test. Since the FPGA's transit time from one task to another has a direct consequence on the system delay, the test must be very fast. Therefore, the test proposed targets only a test of tiles where the majority of the data will be configured and only configurable logic blocks actually used are tested. The technique proposed targets test which is achieved within the fault tolerant system, and is very useful in some critical applications with time and resources constraints.","PeriodicalId":360389,"journal":{"name":"ICM 2001 Proceedings. The 13th International Conference on Microelectronics.","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125019602","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A simple approach for modeling the influence of hot-carrier effect on threshold voltage of MOS transistors 热载子效应对MOS晶体管阈值电压影响的一种简单建模方法
ICM 2001 Proceedings. The 13th International Conference on Microelectronics. Pub Date : 1900-01-01 DOI: 10.1109/ICM.2001.997482
F. Kaçar, A. Kuntman, H. Kuntman
{"title":"A simple approach for modeling the influence of hot-carrier effect on threshold voltage of MOS transistors","authors":"F. Kaçar, A. Kuntman, H. Kuntman","doi":"10.1109/ICM.2001.997482","DOIUrl":"https://doi.org/10.1109/ICM.2001.997482","url":null,"abstract":"Hot-carrier-induced degradation of MOSFET parameters over time is an important reliability concept in modern microcircuits. In this paper, a new simple expression based on the polynomial approximation is proposed for modeling the influence of hot-carrier effects on MOSFET threshold voltage. The method is especially useful to determine the degradation of MOS transistors in analogue building blocks and to predict operational reliability; therefore, it provides new possibilities in analogue IC design.","PeriodicalId":360389,"journal":{"name":"ICM 2001 Proceedings. The 13th International Conference on Microelectronics.","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130813445","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Power bus optimal sizing in presence of power supply noise 电源噪声存在下的电源母线优化尺寸
ICM 2001 Proceedings. The 13th International Conference on Microelectronics. Pub Date : 1900-01-01 DOI: 10.1109/ICM.2001.997500
M. Graziano, G. Masera, G. Piccinini, M. Zamboni
{"title":"Power bus optimal sizing in presence of power supply noise","authors":"M. Graziano, G. Masera, G. Piccinini, M. Zamboni","doi":"10.1109/ICM.2001.997500","DOIUrl":"https://doi.org/10.1109/ICM.2001.997500","url":null,"abstract":"As a consequence of the growing complexity in ultra deep submicron designs, phenomena like IR drops, electromigration and ground bounce are assuming increasing proportions in high performance integrated circuits, compromising their performances and their functionality. This paper suggests a methodology to evaluate power supply noise generation while optimizing power supply bus sizes. Its appropriateness seems to be helpful if applied during the circuit design flow in conjunction with a project tool having as a preeminent target noise reduction.","PeriodicalId":360389,"journal":{"name":"ICM 2001 Proceedings. The 13th International Conference on Microelectronics.","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134601185","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
MEMS inductor in LC receivers for the RF link of cochlear implants 人工耳蜗射频链路LC接收机中的MEMS电感
ICM 2001 Proceedings. The 13th International Conference on Microelectronics. Pub Date : 1900-01-01 DOI: 10.1109/ICM.2001.997517
B. Mezghani, S. Smaoui, M. Masmoudi, C. Dufaza
{"title":"MEMS inductor in LC receivers for the RF link of cochlear implants","authors":"B. Mezghani, S. Smaoui, M. Masmoudi, C. Dufaza","doi":"10.1109/ICM.2001.997517","DOIUrl":"https://doi.org/10.1109/ICM.2001.997517","url":null,"abstract":"In this paper, we present the study and simulation of different micromachined inductor models. We show, from simulation results, that the loss in the output voltage level is mainly due to the series metal resistance of the inductor. The inductor metal width was increased from 1.9 /spl mu/m to 10 /spl mu/m, which decreased the series resistance. The output voltage level increased from 1V to 3V. To further increase the cross sectional area of the inductor metal, a new concept of micromachined inductor on silicon is presented. The new inductor is formed by connecting metal 1 to metal 2, thus a reduction in the series resistance of 70% could be obtained.","PeriodicalId":360389,"journal":{"name":"ICM 2001 Proceedings. The 13th International Conference on Microelectronics.","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134405639","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Recursive and flat partitioning for VLSI circuit design VLSI电路设计中的递归与平面划分
ICM 2001 Proceedings. The 13th International Conference on Microelectronics. Pub Date : 1900-01-01 DOI: 10.1109/ICM.2001.997654
S. Areibi
{"title":"Recursive and flat partitioning for VLSI circuit design","authors":"S. Areibi","doi":"10.1109/ICM.2001.997654","DOIUrl":"https://doi.org/10.1109/ICM.2001.997654","url":null,"abstract":"Circuit partitioning is a subproblem of the physical design phase and considered to be a very important tool for circuit layout. Recent work of Cong and Lim (1998) suggests that multi-way bi-partitioning is more effective than hierarchical bi-partitioning based on a recursive scheme, in addition to the limitation of recursive multi-way partitioners to minimize absorption cost metrics but not hyper-edge cost metrics. In this paper, we use a modified recursive multi-way partitioner to prove that hierarchical bi-partitioning is more effective than multi-way partitioning for both cost metrics. Results obtained indicate that hierarchical bi-partitioning obtains cutsize results that are on average 25% and 55% better than a multiway flat partitioning based on the hyper-edge and absorption costs, respectively. In addition, a combined hierarchical bi-partitioning followed by a multiway flat partitioning scheme improves results on average by 42% for the hyper-edge cost metric.","PeriodicalId":360389,"journal":{"name":"ICM 2001 Proceedings. The 13th International Conference on Microelectronics.","volume":"105 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133145402","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
Noise characterisation in CMOS APS imagers for highly integrated imaging systems 用于高度集成成像系统的CMOS APS成像仪的噪声特性
ICM 2001 Proceedings. The 13th International Conference on Microelectronics. Pub Date : 1900-01-01 DOI: 10.1109/ICM.2001.997479
H. Belahrach, M. Karim, J. Farré
{"title":"Noise characterisation in CMOS APS imagers for highly integrated imaging systems","authors":"H. Belahrach, M. Karim, J. Farré","doi":"10.1109/ICM.2001.997479","DOIUrl":"https://doi.org/10.1109/ICM.2001.997479","url":null,"abstract":"The design of active pixel image sensors (APS) fabricated in traditional CMOS foundries has been a topic of renewed interest in the last several years. The noise reduction is a key issue and often defines the sensitivity or detection limit. In this paper, a thorough noise analysis is made of the expected performance of the APS imagers. White noise and low-frequency (LF) noise sets a fundamental limit on APS performance, especially for low-light applications. Therefore, a detailed theoretical analysis of the in-pixel amplifier and the readout circuit response to the LF noise is investigated. Some experimental LF noise results obtained at room temperature on N-channel MOSFETs fabricated using a 0.7 /spl mu/m CMOS process are presented. We show that the LF noise spectra generated by small area MOSFETs are Lorentzian rather than pure 1/f shape chiefly for the weak inversion mode. Next, using PSPICE simulations, the noise due to the readout circuit during integration is carried out.","PeriodicalId":360389,"journal":{"name":"ICM 2001 Proceedings. The 13th International Conference on Microelectronics.","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121842718","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Digital hardware implementation of sigmoid function and its derivative for artificial neural networks 人工神经网络中sigmoid函数及其导数的数字硬件实现
ICM 2001 Proceedings. The 13th International Conference on Microelectronics. Pub Date : 1900-01-01 DOI: 10.1109/ICM.2001.997519
H. Faiedh, Z. Gafsi, K. Besbes
{"title":"Digital hardware implementation of sigmoid function and its derivative for artificial neural networks","authors":"H. Faiedh, Z. Gafsi, K. Besbes","doi":"10.1109/ICM.2001.997519","DOIUrl":"https://doi.org/10.1109/ICM.2001.997519","url":null,"abstract":"In this paper we propose a polynomial approximation of the sigmoid activation function and its derivative used in artificial neural networks, and we describe the design of the equivalent digital circuit using a floating-point representation for numbers. The simulation of the circuit realized with CMOS technology AMS 0.35/spl mu/m under a frequency of 300 MHz shows the efficiency of the implementation.","PeriodicalId":360389,"journal":{"name":"ICM 2001 Proceedings. The 13th International Conference on Microelectronics.","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124841169","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
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