Recursive and flat partitioning for VLSI circuit design

Abstract

Circuit partitioning is a subproblem of the physical design phase and considered to be a very important tool for circuit layout. Recent work of Cong and Lim (1998) suggests that multi-way bi-partitioning is more effective than hierarchical bi-partitioning based on a recursive scheme, in addition to the limitation of recursive multi-way partitioners to minimize absorption cost metrics but not hyper-edge cost metrics. In this paper, we use a modified recursive multi-way partitioner to prove that hierarchical bi-partitioning is more effective than multi-way partitioning for both cost metrics. Results obtained indicate that hierarchical bi-partitioning obtains cutsize results that are on average 25% and 55% better than a multiway flat partitioning based on the hyper-edge and absorption costs, respectively. In addition, a combined hierarchical bi-partitioning followed by a multiway flat partitioning scheme improves results on average by 42% for the hyper-edge cost metric.