Estimation and optimization of delay in popular CMOS logic styles

Abstract

This paper presents a unified model for delay estimation in various CMOS logic styles. It also derives closed-form optimal transistor sizing formulas for minimizing the delay in each logic style. The paper demonstrates the use of these formulas for delay optimization in mixed logic-style CMOS circuits. Mixing CMOS logic styles in a circuit has the potential of improving performance and reducing energy dissipation and area.