A hardware accelerator for DSP system design: University of Tehran DSP Hardware Emulator (UTDHE)

H.R. Mahdiany, A. Hormati, S. M. Fakhraie
{"title":"A hardware accelerator for DSP system design: University of Tehran DSP Hardware Emulator (UTDHE)","authors":"H.R. Mahdiany, A. Hormati, S. M. Fakhraie","doi":"10.1109/ICM.2001.997507","DOIUrl":null,"url":null,"abstract":"DSP systems play an important role in modern industry and new DSP systems should be designed rapidly to overcome the new necessities that arise. However, the process of designing a DSP system is very time consuming and most of this time is wasted on simulating and debugging of such complex systems. We have designed and implemented a system that makes it possible to emulate and debug large DSP designs (up to 250,000 gates) as fast as possible. With this system, the user can test his or her DSP scheme with fast hardware emulation instead of slow software simulation and as a result reduce time to market significantly. The designed DSP HWE system can emulate complex DSPs that operate at different clock rates and need up to four modules of external memories. It is important to note that low-level simulation of such systems needs a long simulation time, making it impossible to completely simulate and test such designs. As a result of this work, such prohibitive factor has been eliminated.","PeriodicalId":360389,"journal":{"name":"ICM 2001 Proceedings. The 13th International Conference on Microelectronics.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"6","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"ICM 2001 Proceedings. The 13th International Conference on Microelectronics.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICM.2001.997507","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 6

Abstract

DSP systems play an important role in modern industry and new DSP systems should be designed rapidly to overcome the new necessities that arise. However, the process of designing a DSP system is very time consuming and most of this time is wasted on simulating and debugging of such complex systems. We have designed and implemented a system that makes it possible to emulate and debug large DSP designs (up to 250,000 gates) as fast as possible. With this system, the user can test his or her DSP scheme with fast hardware emulation instead of slow software simulation and as a result reduce time to market significantly. The designed DSP HWE system can emulate complex DSPs that operate at different clock rates and need up to four modules of external memories. It is important to note that low-level simulation of such systems needs a long simulation time, making it impossible to completely simulate and test such designs. As a result of this work, such prohibitive factor has been eliminated.
面向DSP系统设计的硬件加速器:德黑兰大学DSP硬件仿真器(UTDHE)
DSP系统在现代工业中发挥着重要的作用,必须迅速设计新的DSP系统以满足新的需求。然而,DSP系统的设计过程非常耗时,大部分时间都浪费在对复杂系统的仿真和调试上。我们设计并实现了一个系统,可以尽可能快地模拟和调试大型DSP设计(多达250,000个门)。使用该系统,用户可以用快速的硬件仿真代替缓慢的软件仿真来测试自己的DSP方案,从而大大缩短了产品上市时间。所设计的DSP HWE系统可以模拟在不同时钟速率下工作的复杂DSP,并且需要多达四个外部存储器模块。值得注意的是,这种系统的低级模拟需要很长的模拟时间,因此不可能完全模拟和测试这种设计。由于这项工作,这种阻碍因素已被消除。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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