A new area-power efficient split-output TSPC CMOS latch for high-speed VLSI applications

Abstract

In this paper, a new True Single-Phase clocked (TSPC) split-output latch is introduced, and compared with existing split-output latches. The comparison is based on the criteria of robustness, area and power efficiency at high speeds. SPICE simulation is used with a 0.5-/spl mu/m CMOS process, to compare four different P-MOS split-output latches at 625 MHz, using a 3.3 V power supply. It is shown that the new split-output latch is more area-power efficient, and significantly more robust, than the existing split-output CMOS latches.