CAD flow for system on chip

The introduction of very high deep sub-micron technology introduces a lot of new problems due to the increase in complexity. In order to handle huge chips containing 40-50 millions of transistors gathered in 30-40 blocks (commonly named IPs), multi clock domains, multi powered analog blocks, routed on 6 metal layers with some wire length measuring up to 3 cm, a hierarchical approach must be set up focusing on verification and timing closure. The author considers the following aspects of the problem: timing, data structures, top-down methodology, design teams, RTL quality, logic design standardization, DFT rules, formal proof, system verification, timing block level sign-off, and physical sign-off.