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1996 IEEE-CAS Region 8 Workshop on Analog and Mixed IC Design. Proceedings最新文献

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A monolithic complex sigma-delta modulator for digital radio 用于数字无线电的单片复杂sigma-delta调制器
1996 IEEE-CAS Region 8 Workshop on Analog and Mixed IC Design. Proceedings Pub Date : 1996-09-13 DOI: 10.1109/AMICD.1996.1296589
A. Swaminathan, M. Snelgrove, S. Jantzi, S. Bazarjani
{"title":"A monolithic complex sigma-delta modulator for digital radio","authors":"A. Swaminathan, M. Snelgrove, S. Jantzi, S. Bazarjani","doi":"10.1109/AMICD.1996.1296589","DOIUrl":"https://doi.org/10.1109/AMICD.1996.1296589","url":null,"abstract":"II. Complex Filtering An architecture for a 1.9 GHz PCS receiver is described. This architecture uses a single IF and a Complex Bandpass Sigma-Delta Modulator (BPEAM) to digitize the signal at the IF. This demonstrates the feasibility of this type of modulator in I/Q radios. Image rejection is then done in DSI? A fourth order XA modulator has been realized in a 0.8um BiCMOS process for the receiver. The modulator is clocked at 4MHz, with a SNR of 48dB for an oversampling ratio (OSR) of 200 and has a power dissipation of 15OmW with a 5V supply. Most filters have transfer functions that contain conjugate poles and zeros because they use real coefficients. A complex filter can be designed that has non-conjugate poles and zeros which takes a complex-valued input and gives a complex-valued output [6][7][8]. This makes it particularly useful for I/Q (real/imaginary) radio applications. r i Xre(2) A re (z ) m Yre(2)","PeriodicalId":356572,"journal":{"name":"1996 IEEE-CAS Region 8 Workshop on Analog and Mixed IC Design. Proceedings","volume":"174 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115445720","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
Coupled relaxation oscillators with highly stable and accurate quadrature outputs 耦合弛豫振荡器，具有高度稳定和精确的正交输出
1996 IEEE-CAS Region 8 Workshop on Analog and Mixed IC Design. Proceedings Pub Date : 1996-09-13 DOI: 10.1109/AMICD.1996.569377
J. Westra, R.T. Godijn, C. Verhoeven, A. V. van Roermund
{"title":"Coupled relaxation oscillators with highly stable and accurate quadrature outputs","authors":"J. Westra, R.T. Godijn, C. Verhoeven, A. V. van Roermund","doi":"10.1109/AMICD.1996.569377","DOIUrl":"https://doi.org/10.1109/AMICD.1996.569377","url":null,"abstract":"Coupled relaxation oscillators can have extremely accurate and stable quadrature outputs. A model is presented to predict the stability of the phase relation. It is confirmed by measurements and shows the power of the concept.","PeriodicalId":356572,"journal":{"name":"1996 IEEE-CAS Region 8 Workshop on Analog and Mixed IC Design. Proceedings","volume":"100 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117232623","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A single-loop second-order /spl Delta//spl Sigma/ frequency discriminator 单回路二阶/spl Delta//spl Sigma/鉴频器
1996 IEEE-CAS Region 8 Workshop on Analog and Mixed IC Design. Proceedings Pub Date : 1996-09-13 DOI: 10.1109/AMICD.1996.569375
W. T. Bax, M. Copeland, T. Riley
{"title":"A single-loop second-order /spl Delta//spl Sigma/ frequency discriminator","authors":"W. T. Bax, M. Copeland, T. Riley","doi":"10.1109/AMICD.1996.569375","DOIUrl":"https://doi.org/10.1109/AMICD.1996.569375","url":null,"abstract":"A new single-loop architecture for a second-order /spl Delta//spl Sigma/ frequency discriminator suitable for RF applications is presented. This architecture can be realized using mostly digital blocks and has several advantages over multi-loop structures which are susceptible to analog non-idealities. A 2 GHz version of the /spl Delta//spl Sigma/ frequency discriminator targeted to wireless mobile applications has been implemented in a 0.8 /spl mu/m BiCMOS process. Measured results show a peak signal-to-noise ratio of 45 dB in a 200 kHz bandwidth.","PeriodicalId":356572,"journal":{"name":"1996 IEEE-CAS Region 8 Workshop on Analog and Mixed IC Design. Proceedings","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121610118","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
High-efficiency low-power one-clock solutions for multi-clock chips and systems 用于多时钟芯片和系统的高效低功耗单时钟解决方案
1996 IEEE-CAS Region 8 Workshop on Analog and Mixed IC Design. Proceedings Pub Date : 1996-09-13 DOI: 10.1109/AMICD.1996.569385
R. Fried
{"title":"High-efficiency low-power one-clock solutions for multi-clock chips and systems","authors":"R. Fried","doi":"10.1109/AMICD.1996.569385","DOIUrl":"https://doi.org/10.1109/AMICD.1996.569385","url":null,"abstract":"This paper presents two basic high-efficiency low-power approaches for driving multi-clock chips and systems from only one external clock source. In the first approach a high-frequency crystal oscillator with reduced power-consumption is used to generate all the system frequencies. For the second approach, a low-power Digital Phase Locked Loop (DPLL) with +/- 100 ps jitter, one-cycle frequency lock-in time and very high frequency multiplication factor is presented.","PeriodicalId":356572,"journal":{"name":"1996 IEEE-CAS Region 8 Workshop on Analog and Mixed IC Design. Proceedings","volume":"63 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115794579","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
New low-power ICO/VCO with double cross-coupled high-speed architecture 新型低功耗ICO/VCO双交叉耦合高速架构
1996 IEEE-CAS Region 8 Workshop on Analog and Mixed IC Design. Proceedings Pub Date : 1996-09-13 DOI: 10.1109/AMICD.1996.569370
N. Tchamov, A. Popov, P. Jarske
{"title":"New low-power ICO/VCO with double cross-coupled high-speed architecture","authors":"N. Tchamov, A. Popov, P. Jarske","doi":"10.1109/AMICD.1996.569370","DOIUrl":"https://doi.org/10.1109/AMICD.1996.569370","url":null,"abstract":"New circuits of high-speed multivibrators have been developed and subsequently used to create a new ICO/VCO circuit. While implemented on 0.8 /spl mu/m BiCMOS (14 GHz NPN) an amplitude on the symmetrical output of 550 mV at 2 GHz, with consumption less than 3.3 mW from 1.5 V power supply can be easily achieved. The control ability of the ICO is about 2.6 MHz//spl mu/A. The low phase-noise makes the circuit also suitable for building high-speed PLLs for various applications in communications and microprocessors.","PeriodicalId":356572,"journal":{"name":"1996 IEEE-CAS Region 8 Workshop on Analog and Mixed IC Design. Proceedings","volume":"211 ","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133490136","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Two VLSI CMOS ICs for digital X-ray 2-D imaging system: low noise front-end amplifier and 80 MHz digital encoder interface 两个用于数字x射线二维成像系统的VLSI CMOS ic:低噪声前端放大器和80 MHz数字编码器接口
1996 IEEE-CAS Region 8 Workshop on Analog and Mixed IC Design. Proceedings Pub Date : 1996-09-13 DOI: 10.1109/AMICD.1996.569383
R. Marchesini, R. Beccherle, M. G. Bisogni, A. Cisternino, A. Del Guerra, M. Folli, I. Kipnis, V. Rosso, R. Tipiccione
{"title":"Two VLSI CMOS ICs for digital X-ray 2-D imaging system: low noise front-end amplifier and 80 MHz digital encoder interface","authors":"R. Marchesini, R. Beccherle, M. G. Bisogni, A. Cisternino, A. Del Guerra, M. Folli, I. Kipnis, V. Rosso, R. Tipiccione","doi":"10.1109/AMICD.1996.569383","DOIUrl":"https://doi.org/10.1109/AMICD.1996.569383","url":null,"abstract":"We describe a VLSI-based data acquisition to perform X-Y coincidences with a two side microstrip digital detector, optimized for applications in digital mammography. A two components chip set is described in detail: a low noise Front-End analog amplifier and an 80 MHz synchronous digital encoder. These two components can be used to solve the problems arising with the use of a large number of channels and low signal amplitude as in our application.","PeriodicalId":356572,"journal":{"name":"1996 IEEE-CAS Region 8 Workshop on Analog and Mixed IC Design. Proceedings","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132839344","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Challenges in analog IC design submicron CMOS technologies 亚微米CMOS技术在模拟IC设计中的挑战
1996 IEEE-CAS Region 8 Workshop on Analog and Mixed IC Design. Proceedings Pub Date : 1996-09-13 DOI: 10.1109/AMICD.1996.569388
W. Sansen
{"title":"Challenges in analog IC design submicron CMOS technologies","authors":"W. Sansen","doi":"10.1109/AMICD.1996.569388","DOIUrl":"https://doi.org/10.1109/AMICD.1996.569388","url":null,"abstract":"In submicron CMOS devices, short-channel effects lead to shifts in threshold voltage, increased mismatch and noise. The velocity saturation limits the obtainable transconductance and hence also the high-speed performance. Lower supply voltages require the operational amplifier building block to operate rail-to-rail. In delta-sigma converters this leads to very-low-power converters. Considerable attention is given to circuit design for telecommunication applications, in which the inductor is making a comeback. The ultimate challenge-of analog design however is the cointegration with digital blocks, causing coupling noise and requiring sophisticated tools.","PeriodicalId":356572,"journal":{"name":"1996 IEEE-CAS Region 8 Workshop on Analog and Mixed IC Design. Proceedings","volume":"485 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116691841","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 88
A 3 V second order sigma delta modulator using a pseudo bilinear switched current integrator 一个使用伪双线性开关电流积分器的3v二阶σ δ调制器
1996 IEEE-CAS Region 8 Workshop on Analog and Mixed IC Design. Proceedings Pub Date : 1996-09-13 DOI: 10.1109/AMICD.1996.569395
M. Loulou, H. Traff, P. Marchegay
{"title":"A 3 V second order sigma delta modulator using a pseudo bilinear switched current integrator","authors":"M. Loulou, H. Traff, P. Marchegay","doi":"10.1109/AMICD.1996.569395","DOIUrl":"https://doi.org/10.1109/AMICD.1996.569395","url":null,"abstract":"This paper presents the design of a 3 V switched current second order sigma-delta modulator. The core element is a fully differential pseudo bilinear switched current integrator with current mode common mode feedback. The modulator is implemented in a 1.2 /spl mu/m double-metal digital CMOS process. Measurement results are presented and show a resolution of 11 bits.","PeriodicalId":356572,"journal":{"name":"1996 IEEE-CAS Region 8 Workshop on Analog and Mixed IC Design. Proceedings","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123986915","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Front-end electronics integrated on high resistivity semiconductor radiation detectors 集成在高电阻率半导体辐射探测器上的前端电子器件
1996 IEEE-CAS Region 8 Workshop on Analog and Mixed IC Design. Proceedings Pub Date : 1996-09-13 DOI: 10.1109/AMICD.1996.569402
L. Fasoli, C. Fiorini, A. Longoni, M. Sampietro, P. Lechner, L. Struder
{"title":"Front-end electronics integrated on high resistivity semiconductor radiation detectors","authors":"L. Fasoli, C. Fiorini, A. Longoni, M. Sampietro, P. Lechner, L. Struder","doi":"10.1109/AMICD.1996.569402","DOIUrl":"https://doi.org/10.1109/AMICD.1996.569402","url":null,"abstract":"Two different front-end FETs integrated on high-resistivity silicon detectors are presented: an implanted n-type JFET and a p-type JFET. These devices use different mechanisms to discharge the detector leakage current and the signal charge through the transistors electrodes. The two transistors have been integrated in the anode region of a semiconductor drift detector and tested experimentally. Spectroscopy measurements, also shown in the paper, have been made in order to determine the characteristic noise parameters of the transistors and to compare the performances of the two solutions.","PeriodicalId":356572,"journal":{"name":"1996 IEEE-CAS Region 8 Workshop on Analog and Mixed IC Design. Proceedings","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121643302","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A 2-path /spl Sigma//spl Delta/ modulator for bandpass applications 用于带通应用的2路/spl Sigma//spl Delta/调制器
1996 IEEE-CAS Region 8 Workshop on Analog and Mixed IC Design. Proceedings Pub Date : 1996-09-13 DOI: 10.1109/AMICD.1996.569392
E. André, D. Morche, F. Balestro, P. Senn
{"title":"A 2-path /spl Sigma//spl Delta/ modulator for bandpass applications","authors":"E. André, D. Morche, F. Balestro, P. Senn","doi":"10.1109/AMICD.1996.569392","DOIUrl":"https://doi.org/10.1109/AMICD.1996.569392","url":null,"abstract":"This article presents a low-power bandpass sigma-delta modulator using a multibit quantizer (9 levels) and switched-capacitor DAC. The circuit is being manufactured in the 0.5 /spl mu/m CMOS technology to operate with a 3.3-/spl nu/ power supply. The sampling frequency Fs=24.576 MHz has been chosen to be equal to 4 times the intermediate frequency fo=6.144 MHz. Computer simulations revealed a SNR=60 dB (10 bits) with a bandwith of 1.536 MHz, that is to say OSR=8. The power consumption is evaluated at 25 mW and the integration surface at about 2 mm/sup 2/. The performance evaluation is based on the test results of a previous circuit designed on the same basis (a 1-bit 4th-order bandpass /spl Sigma//spl Delta/ modulator).","PeriodicalId":356572,"journal":{"name":"1996 IEEE-CAS Region 8 Workshop on Analog and Mixed IC Design. Proceedings","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116474224","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
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