High-efficiency low-power one-clock solutions for multi-clock chips and systems

Abstract

This paper presents two basic high-efficiency low-power approaches for driving multi-clock chips and systems from only one external clock source. In the first approach a high-frequency crystal oscillator with reduced power-consumption is used to generate all the system frequencies. For the second approach, a low-power Digital Phase Locked Loop (DPLL) with +/- 100 ps jitter, one-cycle frequency lock-in time and very high frequency multiplication factor is presented.