发布求助
文献互助 智能选刊 最新文献

1996 IEEE-CAS Region 8 Workshop on Analog and Mixed IC Design. Proceedings最新文献

筛选
英文 中文
An efficient and high-performances CMOS op amp with rail-to-rail mode and high CMRR 具有轨对轨模式和高CMRR的高效高性能CMOS运放
1996 IEEE-CAS Region 8 Workshop on Analog and Mixed IC Design. Proceedings Pub Date : 1996-09-13 DOI: 10.1109/AMICD.1996.569397
G. Klisnick, M. Redon
{"title":"An efficient and high-performances CMOS op amp with rail-to-rail mode and high CMRR","authors":"G. Klisnick, M. Redon","doi":"10.1109/AMICD.1996.569397","DOIUrl":"https://doi.org/10.1109/AMICD.1996.569397","url":null,"abstract":"In this paper, we present a new structure of a CMOS Op Amp offering high performances differential frequency response with high CMRR, high slew rate and input/output rail-to-rail mode. These performances are due both to a new efficient gain stage with a compact layout and to a simple way to obtain a high CMRR. Simulation experiments have been performed with three different (0.8 /spl mu/m, 1.2 /spl mu/m, 2.4 /spl mu/m) CMOS technologies. In particular for the 0.8 /spl mu/m one, the main performances-under single 5 V power supply are a unity gain bandwidth of 40 MHz, a phase margin of 63 degrees, a slew rate of 60 V//spl mu/s, all performed on heavy load such as 2.5 k/spl Omega//spl par/20 pF. Simulated results have been experimentally confirmed for the 2.4 /spl mu/m CMOS technology for which we have measured a low frequency CMRR of 100 dB.","PeriodicalId":356572,"journal":{"name":"1996 IEEE-CAS Region 8 Workshop on Analog and Mixed IC Design. Proceedings","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114674037","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Design of a voltage-to-current converting interface for current-mode video signal processing applications 电流模式视频信号处理应用的电压-电流转换接口设计
1996 IEEE-CAS Region 8 Workshop on Analog and Mixed IC Design. Proceedings Pub Date : 1996-09-13 DOI: 10.1109/AMICD.1996.569386
F. Maloberti, R. Rivoir
{"title":"Design of a voltage-to-current converting interface for current-mode video signal processing applications","authors":"F. Maloberti, R. Rivoir","doi":"10.1109/AMICD.1996.569386","DOIUrl":"https://doi.org/10.1109/AMICD.1996.569386","url":null,"abstract":"Voltage-to-current converters (VICs) are starting to be extensively used in video speed current-mode analog circuits, especially in A/D converters, as internal building blocks or external interfaces with voltage-mode signals. Despite the important role played by VIC's in video signal processing systems, until now no design examples nor experimental results on video rate VIC's have been reported. The purpose of this paper is to present the design of a newly developed VI converter, suitable for interfacing 8-b current-mode circuits operating at video frequencies with voltage signals. A test circuit has been fabricated in 0.7-/spl mu/m, 5-V single-supply CMOS digital process.","PeriodicalId":356572,"journal":{"name":"1996 IEEE-CAS Region 8 Workshop on Analog and Mixed IC Design. Proceedings","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122303316","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Current-mode up-converting D/A-interface for mobile communication transmitter applications 用于移动通信发射机应用的电流模式上转换D/ a接口
1996 IEEE-CAS Region 8 Workshop on Analog and Mixed IC Design. Proceedings Pub Date : 1996-09-13 DOI: 10.1109/AMICD.1996.569374
K. Koli, K. Halonen, E. Tiiliharju
{"title":"Current-mode up-converting D/A-interface for mobile communication transmitter applications","authors":"K. Koli, K. Halonen, E. Tiiliharju","doi":"10.1109/AMICD.1996.569374","DOIUrl":"https://doi.org/10.1109/AMICD.1996.569374","url":null,"abstract":"A low voltage low power current-mode D/A interface with smoothing filter and upconversion mixer is presented. The D/A-converter is a binary weighted current-switching converter with 8-bit resolution. The uni-directional D/A-output currents are converted to bi-directional input currents for a differential current-mode 1 MHz low-pass filter by a common-mode feedforward circuit. The smoothing filter and current gain amplifier use high-gain current amplifiers using dynamically biased low distortion transconductance output stage. The filtered and amplified current is then fed to a current-switching mixer with off-chip loads. The filter operates with down to a 3 V supply voltage while the D/A-converter can operate even with 2.5 V supply. The harmonic distortion of the filter is typically lower than -50 dBc and thus more than 8-bit spurious free range can be achieved by oversampling.","PeriodicalId":356572,"journal":{"name":"1996 IEEE-CAS Region 8 Workshop on Analog and Mixed IC Design. Proceedings","volume":"123 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122482189","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Programmable IIR filter using bitstream processing 使用比特流处理的可编程IIR滤波器
1996 IEEE-CAS Region 8 Workshop on Analog and Mixed IC Design. Proceedings Pub Date : 1996-09-13 DOI: 10.1109/AMICD.1996.569399
C. Azeredo Leme, L. Fernandes, J. Franca
{"title":"Programmable IIR filter using bitstream processing","authors":"C. Azeredo Leme, L. Fernandes, J. Franca","doi":"10.1109/AMICD.1996.569399","DOIUrl":"https://doi.org/10.1109/AMICD.1996.569399","url":null,"abstract":"This paper presents a compact CMOS realization of cascaded biquad digital filters using 2nd order /spl Delta//spl Sigma/ modulators requiring no multibit multiplier. A bitstream biquad is derived with just one /spl Delta//spl Sigma/ modulator for each pair of poles which leads to a very compact implementation. No significant degradation of sensitivity nor of dynamic range is observed. The analog interfaces are highly simplified due to the bitstream input and output formats.","PeriodicalId":356572,"journal":{"name":"1996 IEEE-CAS Region 8 Workshop on Analog and Mixed IC Design. Proceedings","volume":"98 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133975857","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Embedded systems: past experience and future demands 嵌入式系统:过去的经验和未来的需求
1996 IEEE-CAS Region 8 Workshop on Analog and Mixed IC Design. Proceedings Pub Date : 1996-09-13 DOI: 10.1109/AMICD.1996.569378
D. Rossi
{"title":"Embedded systems: past experience and future demands","authors":"D. Rossi","doi":"10.1109/AMICD.1996.569378","DOIUrl":"https://doi.org/10.1109/AMICD.1996.569378","url":null,"abstract":"The development of mixed technologies, the technological progress that step by step moved the limits of CMOS transistors when used in analog applications, the demand for higher integration, increased reliability and lower system cost have recently led to the development of integrated circuits more complex and sophisticated. To meet these insatiable needs, combining analog and digital functions into a single chip has been an unavoidable path to follow. As a matter of fact, analog and digital real time signal processing is compatible now to a single chip solution. This integration, far for being a mere collage of already circuits and macros (in fact, if was until the early '80s that ICs vendors attempted commercial mixed-mode designs) asked the ICs design community to cultivate technologies where the analog and digital \"incompatibilties\" can, on the contrary, coexist. This paper, in the attempt to deal with the genesis and evolution of mixed-mode ICs wants, through practical examples, firstly to report about the increasing complexity of this kind of products (from a simple digital interface to DSPs and micros embedded together with analog functions) and secondly, to describe the obstacles (ranging from technology to CAD) still challenging the ICs designer and often hiding the real productivity of mixed-mode integrated circuits.","PeriodicalId":356572,"journal":{"name":"1996 IEEE-CAS Region 8 Workshop on Analog and Mixed IC Design. Proceedings","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122818735","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Random capacitance ratio error effects in the frequency response of switched-capacitor filters 随机电容比误差对开关电容滤波器频率响应的影响
1996 IEEE-CAS Region 8 Workshop on Analog and Mixed IC Design. Proceedings Pub Date : 1996-09-13 DOI: 10.1109/AMICD.1996.569400
A. Petraglia
{"title":"Random capacitance ratio error effects in the frequency response of switched-capacitor filters","authors":"A. Petraglia","doi":"10.1109/AMICD.1996.569400","DOIUrl":"https://doi.org/10.1109/AMICD.1996.569400","url":null,"abstract":"This paper considers the effects of random, Gaussian distributed, capacitance ratio errors in the the frequency response of switched-capacitor filters. Closed-form expressions are given for the mean and the standard deviation of the error in the frequency response of a large class of filter approximations. Experimental results, obtained through simulations using the Monte Carlo method of computer analysis, are presented to verify the key formulas obtained in the theoretical study.","PeriodicalId":356572,"journal":{"name":"1996 IEEE-CAS Region 8 Workshop on Analog and Mixed IC Design. Proceedings","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114790591","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
An integrated 100 MHz to 1 GHz I/Q modulator with CML phase shifter 集成100 MHz至1 GHz I/Q调制器与CML移相器
1996 IEEE-CAS Region 8 Workshop on Analog and Mixed IC Design. Proceedings Pub Date : 1996-09-13 DOI: 10.1109/AMICD.1996.569368
J. Hakkinen, T. Rahkonen, J. Kostamovaara
{"title":"An integrated 100 MHz to 1 GHz I/Q modulator with CML phase shifter","authors":"J. Hakkinen, T. Rahkonen, J. Kostamovaara","doi":"10.1109/AMICD.1996.569368","DOIUrl":"https://doi.org/10.1109/AMICD.1996.569368","url":null,"abstract":"A direct I/Q modulator suitable for operation at output frequencies from 100 MHz to 1 GHz and baseband frequencies from 60 to 500 kHz is fabricated in a 0.8 /spl mu/m BiCMOS process. The modulator uses a phase shifter topology based on digital CML latches. The circuit operates from a single 5 V supply and it consumes about 100 mA. The circuit size is 2.0 mm/spl times/2.0 mm and it is packed in a 28 pin SOIC. According to measurements, the output power is -11/spl plusmn/0.5 dBm at 100 MHz and -15/spl plusmn/ 2.25 dBm at 950 MHz over the temperature range of -10 to +85/spl deg/C. LO suppression is roughly 38 dBc and image rejection 41 dBc.","PeriodicalId":356572,"journal":{"name":"1996 IEEE-CAS Region 8 Workshop on Analog and Mixed IC Design. Proceedings","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132076980","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A low power 10-bit 300 kS/s RSD coded pipeline A/D-converter 低功耗10位300ks /s RSD编码流水线A/ d转换器
1996 IEEE-CAS Region 8 Workshop on Analog and Mixed IC Design. Proceedings Pub Date : 1996-09-13 DOI: 10.1109/AMICD.1996.569390
A. Mantyniemi, T. Rahkonen, A. Ruha
{"title":"A low power 10-bit 300 kS/s RSD coded pipeline A/D-converter","authors":"A. Mantyniemi, T. Rahkonen, A. Ruha","doi":"10.1109/AMICD.1996.569390","DOIUrl":"https://doi.org/10.1109/AMICD.1996.569390","url":null,"abstract":"This paper describes a 10-bit 300 kS/s analog-to-digital converter fabricated in a 0.8-/spl mu/m CMOS technology. The main objective was to minimise the power consumption of the circuit. This was achieved by using an interleaved pipeline structure with only one operational amplifier per stage. The current consumption of the converter circuit is 2 mA from 2.7 V power supply when using a power saving scheme in which the resolution per stage is moderately relaxed towards the LSB. The digital RSD (Redundant Signed Digit) principle is used to correct the errors caused by the mismatch in the gain factor 2 and the comparator offsets. The measured SNR was 58.5 dB, ENOB 9.4 bits, typical INL +/-1.5 LSB and DNL +/-0.5 LSB. The active chip area is 1.3 mm/sup 2/, excluding pads.","PeriodicalId":356572,"journal":{"name":"1996 IEEE-CAS Region 8 Workshop on Analog and Mixed IC Design. Proceedings","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129312672","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Future terminals: Which RF and analog processes? 未来终端:哪种射频和模拟过程?
1996 IEEE-CAS Region 8 Workshop on Analog and Mixed IC Design. Proceedings Pub Date : 1996-09-13 DOI: 10.1109/AMICD.1996.569367
F. Durufle, F.R. Humbert, R. Rolland
{"title":"Future terminals: Which RF and analog processes?","authors":"F. Durufle, F.R. Humbert, R. Rolland","doi":"10.1109/AMICD.1996.569367","DOIUrl":"https://doi.org/10.1109/AMICD.1996.569367","url":null,"abstract":"Large quantities and reduced costs: in the field of telecommunications, the terminal market is going to pull up the semiconductor market. The development in the direction of silicon-based systems is clear. The equipment manufacturer has to improve his expertise.","PeriodicalId":356572,"journal":{"name":"1996 IEEE-CAS Region 8 Workshop on Analog and Mixed IC Design. Proceedings","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123883339","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Automatic extraction of higher order interconnect parasitics for device level simulators for VHSIC applications 用于VHSIC应用的器件级模拟器的高阶互连寄生的自动提取
1996 IEEE-CAS Region 8 Workshop on Analog and Mixed IC Design. Proceedings Pub Date : 1996-09-13 DOI: 10.1109/AMICD.1996.569380
M. Mokhtari, T. Juhola, G. Schuppener, F. Sellberg
{"title":"Automatic extraction of higher order interconnect parasitics for device level simulators for VHSIC applications","authors":"M. Mokhtari, T. Juhola, G. Schuppener, F. Sellberg","doi":"10.1109/AMICD.1996.569380","DOIUrl":"https://doi.org/10.1109/AMICD.1996.569380","url":null,"abstract":"The necessary routines for extraction of interconnect parasitics have been implemented in Cadence DFWII environment. The implementation allows choice of parasitics based on \"pure-capacitive\", \"RC-\" or third order \"LRC-\" filter. Eye-diagram simulations on CMOS and bipolar gates on Si and HBT gates on InP, emulating MSI Very High Speed circuits, have shown that \"LRC\"-extraction of the power-lines in the case of CMOS in the GHz region is vital in predicting the circuit behaviour. The bipolar test-bed has shown considerably less sensitivity to power-lines. The signal path is more relevant for LRC-extraction in the latter.","PeriodicalId":356572,"journal":{"name":"1996 IEEE-CAS Region 8 Workshop on Analog and Mixed IC Design. Proceedings","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124288483","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
下一页 尾页
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整，为了账户安全，请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
请完成安全验证×
相关产品
×
本文献相关产品
联系我们：info@booksci.cn Book学术提供免费学术资源搜索服务，方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号：481959085
Book学术官方微信