{"title":"低功耗10位300ks /s RSD编码流水线A/ d转换器","authors":"A. Mantyniemi, T. Rahkonen, A. Ruha","doi":"10.1109/AMICD.1996.569390","DOIUrl":null,"url":null,"abstract":"This paper describes a 10-bit 300 kS/s analog-to-digital converter fabricated in a 0.8-/spl mu/m CMOS technology. The main objective was to minimise the power consumption of the circuit. This was achieved by using an interleaved pipeline structure with only one operational amplifier per stage. The current consumption of the converter circuit is 2 mA from 2.7 V power supply when using a power saving scheme in which the resolution per stage is moderately relaxed towards the LSB. The digital RSD (Redundant Signed Digit) principle is used to correct the errors caused by the mismatch in the gain factor 2 and the comparator offsets. The measured SNR was 58.5 dB, ENOB 9.4 bits, typical INL +/-1.5 LSB and DNL +/-0.5 LSB. The active chip area is 1.3 mm/sup 2/, excluding pads.","PeriodicalId":356572,"journal":{"name":"1996 IEEE-CAS Region 8 Workshop on Analog and Mixed IC Design. Proceedings","volume":"26 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1996-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":"{\"title\":\"A low power 10-bit 300 kS/s RSD coded pipeline A/D-converter\",\"authors\":\"A. Mantyniemi, T. Rahkonen, A. Ruha\",\"doi\":\"10.1109/AMICD.1996.569390\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper describes a 10-bit 300 kS/s analog-to-digital converter fabricated in a 0.8-/spl mu/m CMOS technology. The main objective was to minimise the power consumption of the circuit. This was achieved by using an interleaved pipeline structure with only one operational amplifier per stage. The current consumption of the converter circuit is 2 mA from 2.7 V power supply when using a power saving scheme in which the resolution per stage is moderately relaxed towards the LSB. The digital RSD (Redundant Signed Digit) principle is used to correct the errors caused by the mismatch in the gain factor 2 and the comparator offsets. The measured SNR was 58.5 dB, ENOB 9.4 bits, typical INL +/-1.5 LSB and DNL +/-0.5 LSB. The active chip area is 1.3 mm/sup 2/, excluding pads.\",\"PeriodicalId\":356572,\"journal\":{\"name\":\"1996 IEEE-CAS Region 8 Workshop on Analog and Mixed IC Design. Proceedings\",\"volume\":\"26 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1996-09-13\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"4\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"1996 IEEE-CAS Region 8 Workshop on Analog and Mixed IC Design. Proceedings\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/AMICD.1996.569390\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"1996 IEEE-CAS Region 8 Workshop on Analog and Mixed IC Design. Proceedings","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/AMICD.1996.569390","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A low power 10-bit 300 kS/s RSD coded pipeline A/D-converter
This paper describes a 10-bit 300 kS/s analog-to-digital converter fabricated in a 0.8-/spl mu/m CMOS technology. The main objective was to minimise the power consumption of the circuit. This was achieved by using an interleaved pipeline structure with only one operational amplifier per stage. The current consumption of the converter circuit is 2 mA from 2.7 V power supply when using a power saving scheme in which the resolution per stage is moderately relaxed towards the LSB. The digital RSD (Redundant Signed Digit) principle is used to correct the errors caused by the mismatch in the gain factor 2 and the comparator offsets. The measured SNR was 58.5 dB, ENOB 9.4 bits, typical INL +/-1.5 LSB and DNL +/-0.5 LSB. The active chip area is 1.3 mm/sup 2/, excluding pads.
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