{"title":"使用比特流处理的可编程IIR滤波器","authors":"C. Azeredo Leme, L. Fernandes, J. Franca","doi":"10.1109/AMICD.1996.569399","DOIUrl":null,"url":null,"abstract":"This paper presents a compact CMOS realization of cascaded biquad digital filters using 2nd order /spl Delta//spl Sigma/ modulators requiring no multibit multiplier. A bitstream biquad is derived with just one /spl Delta//spl Sigma/ modulator for each pair of poles which leads to a very compact implementation. No significant degradation of sensitivity nor of dynamic range is observed. The analog interfaces are highly simplified due to the bitstream input and output formats.","PeriodicalId":356572,"journal":{"name":"1996 IEEE-CAS Region 8 Workshop on Analog and Mixed IC Design. Proceedings","volume":"98 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1996-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Programmable IIR filter using bitstream processing\",\"authors\":\"C. Azeredo Leme, L. Fernandes, J. Franca\",\"doi\":\"10.1109/AMICD.1996.569399\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents a compact CMOS realization of cascaded biquad digital filters using 2nd order /spl Delta//spl Sigma/ modulators requiring no multibit multiplier. A bitstream biquad is derived with just one /spl Delta//spl Sigma/ modulator for each pair of poles which leads to a very compact implementation. No significant degradation of sensitivity nor of dynamic range is observed. The analog interfaces are highly simplified due to the bitstream input and output formats.\",\"PeriodicalId\":356572,\"journal\":{\"name\":\"1996 IEEE-CAS Region 8 Workshop on Analog and Mixed IC Design. Proceedings\",\"volume\":\"98 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1996-09-13\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"1996 IEEE-CAS Region 8 Workshop on Analog and Mixed IC Design. Proceedings\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/AMICD.1996.569399\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"1996 IEEE-CAS Region 8 Workshop on Analog and Mixed IC Design. Proceedings","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/AMICD.1996.569399","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Programmable IIR filter using bitstream processing
This paper presents a compact CMOS realization of cascaded biquad digital filters using 2nd order /spl Delta//spl Sigma/ modulators requiring no multibit multiplier. A bitstream biquad is derived with just one /spl Delta//spl Sigma/ modulator for each pair of poles which leads to a very compact implementation. No significant degradation of sensitivity nor of dynamic range is observed. The analog interfaces are highly simplified due to the bitstream input and output formats.
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