An integrated 100 MHz to 1 GHz I/Q modulator with CML phase shifter

J. Hakkinen, T. Rahkonen, J. Kostamovaara
{"title":"An integrated 100 MHz to 1 GHz I/Q modulator with CML phase shifter","authors":"J. Hakkinen, T. Rahkonen, J. Kostamovaara","doi":"10.1109/AMICD.1996.569368","DOIUrl":null,"url":null,"abstract":"A direct I/Q modulator suitable for operation at output frequencies from 100 MHz to 1 GHz and baseband frequencies from 60 to 500 kHz is fabricated in a 0.8 /spl mu/m BiCMOS process. The modulator uses a phase shifter topology based on digital CML latches. The circuit operates from a single 5 V supply and it consumes about 100 mA. The circuit size is 2.0 mm/spl times/2.0 mm and it is packed in a 28 pin SOIC. According to measurements, the output power is -11/spl plusmn/0.5 dBm at 100 MHz and -15/spl plusmn/ 2.25 dBm at 950 MHz over the temperature range of -10 to +85/spl deg/C. LO suppression is roughly 38 dBc and image rejection 41 dBc.","PeriodicalId":356572,"journal":{"name":"1996 IEEE-CAS Region 8 Workshop on Analog and Mixed IC Design. Proceedings","volume":"30 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1996-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"1996 IEEE-CAS Region 8 Workshop on Analog and Mixed IC Design. Proceedings","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/AMICD.1996.569368","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1

Abstract

A direct I/Q modulator suitable for operation at output frequencies from 100 MHz to 1 GHz and baseband frequencies from 60 to 500 kHz is fabricated in a 0.8 /spl mu/m BiCMOS process. The modulator uses a phase shifter topology based on digital CML latches. The circuit operates from a single 5 V supply and it consumes about 100 mA. The circuit size is 2.0 mm/spl times/2.0 mm and it is packed in a 28 pin SOIC. According to measurements, the output power is -11/spl plusmn/0.5 dBm at 100 MHz and -15/spl plusmn/ 2.25 dBm at 950 MHz over the temperature range of -10 to +85/spl deg/C. LO suppression is roughly 38 dBc and image rejection 41 dBc.
集成100 MHz至1 GHz I/Q调制器与CML移相器
在0.8 /spl mu/m BiCMOS工艺中,制作了适合于输出频率为100 MHz至1 GHz和基带频率为60至500 kHz的直接I/Q调制器。调制器采用基于数字CML锁存器的移相器拓扑结构。该电路从单个5v电源运行,它消耗约100毫安。电路尺寸为2.0 mm/spl倍/2.0 mm,封装在28引脚SOIC中。根据测量,在100 MHz时输出功率为-11/spl plusmn/0.5 dBm,在950 MHz时输出功率为-15/spl plusmn/ 2.25 dBm,温度范围为-10至+85/spl℃/C。LO抑制约为38 dBc,图像抑制约为41 dBc。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
求助全文
约1分钟内获得全文 求助全文
来源期刊
自引率
0.00%
发文量
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
确定
请完成安全验证×
copy
已复制链接
快去分享给好友吧!
我知道了
右上角分享
点击右上角分享
0
联系我们:info@booksci.cn Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术官方微信