Automatic extraction of higher order interconnect parasitics for device level simulators for VHSIC applications

Abstract

The necessary routines for extraction of interconnect parasitics have been implemented in Cadence DFWII environment. The implementation allows choice of parasitics based on "pure-capacitive", "RC-" or third order "LRC-" filter. Eye-diagram simulations on CMOS and bipolar gates on Si and HBT gates on InP, emulating MSI Very High Speed circuits, have shown that "LRC"-extraction of the power-lines in the case of CMOS in the GHz region is vital in predicting the circuit behaviour. The bipolar test-bed has shown considerably less sensitivity to power-lines. The signal path is more relevant for LRC-extraction in the latter.